Semiconductor memory and nonvolatile memory

ABSTRACT

According to one embodiment, a semiconductor memory includes: a memory group including a plurality of memory cells configured to store a plurality of bits of data in three or more plurality of states; a word line coupled to the plurality of memory cells; and a first circuit configured to convert one external address received from an external controller into a plurality of internal addresses, wherein a first page size of page data of the memory group is smaller than a second page

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2020-192523, filed Nov. 19, 2020; No.2020-214800, filed Dec. 24, 2020; and No. 2021-138120, filed Aug. 26,2021, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor memoryand a nonvolatile memory.

BACKGROUND

As a memory chip mounted on a memory system, a semiconductor memoryusing a NAND flash memory is known.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a memory system including a semiconductormemory according to a first embodiment.

FIG. 2 is a block diagram of the semiconductor memory according to thefirst embodiment.

FIG. 3 is a circuit diagram of a memory cell array included in thesemiconductor memory according to the first embodiment.

FIG. 4 is a cross-sectional view of the memory cell array included inthe semiconductor memory according to the first embodiment.

FIG. 5 is a block diagram of a sense amplifier and a page bufferincluded in the semiconductor memory according to the first embodiment.

FIG. 6 is a perspective view of the semiconductor memory according tothe first embodiment.

FIG. 7 is a diagram showing a relationship between threshold voltagedistributions and data allocations of memory cell transistors in thesemiconductor memory according to the first embodiment.

FIG. 8 is a diagram explaining a flow of a conversion operation of alogical page address and a physical page address in the semiconductormemory according to the first embodiment.

FIG. 9 is a diagram showing a logical page data allocation with respectto a physical page in the semiconductor memory according to the firstembodiment.

FIG. 10 is a flowchart showing a read operation of the semiconductormemory according to the first embodiment.

FIG. 11 is a flowchart showing a read operation of the semiconductormemory according to the first embodiment.

FIG. 12 is a timing chart showing a voltage of a selected word line in aread operation of a logical first page in the semiconductor memoryaccording to the first embodiment.

FIG. 13 is a timing chart showing a voltage of a selected word line in aread operation of a logical second page in the semiconductor memoryaccording to the first embodiment.

FIG. 14 is a command sequence of a read operation of the logical firstpage in the semiconductor memory according to the first embodiment.

FIG. 15 is a command sequence of a read operation of the logical secondpage in the semiconductor memory according to the first embodiment.

FIG. 16 is a flow chart showing a write operation of the semiconductormemory according to the first embodiment.

FIG. 17 is a flow chart showing a write operation of the semiconductormemory according to the first embodiment.

FIG. 18 is a command sequence of a full sequence write operation in thesemiconductor memory according to the first embodiment.

FIG. 19 is a table showing data allocations to each state in asemiconductor memory according to a first example of a secondembodiment.

FIG. 20 is a table showing data allocations to each state in asemiconductor memory according to a second example of the secondembodiment.

FIG. 21 is a table showing data allocations to each state in asemiconductor memory according to a third example of the secondembodiment

FIG. 22 is a table showing data allocations to each state in asemiconductor memory according to a fourth example of the secondembodiment.

FIG. 23 is a table showing data allocations to each state in asemiconductor memory according to a fifth example of the secondembodiment.

FIG. 24 is a table showing data allocations to each state in asemiconductor memory according to a sixth example of the secondembodiment.

FIG. 25 is a table showing data allocations to each state in asemiconductor memory according to a seventh example of the secondembodiment.

FIG. 26 is a command sequence of a read operation of a logical firstpage in a semiconductor memory according to a first example of a thirdembodiment.

FIG. 27 is a command sequence of a read operation of a logical secondpage in the semiconductor memory according to the first example of thethird embodiment.

FIG. 28 is a command sequence of a sequential read operation in asemiconductor memory according to a second example of the thirdembodiment.

FIG. 29 is a diagram showing a relationship between threshold voltagedistributions and data allocations of memory cell transistors in asemiconductor memory according to a fourth embodiment.

FIG. 30 is a diagram explaining a flow of a conversion operation of alogical page address and a physical page address in the semiconductormemory according to the fourth embodiment.

FIG. 31 is a diagram showing a logical page data allocation with respectto a physical page in the semiconductor memory according to the fourthembodiment.

FIG. 32 is a flowchart showing a read operation of the semiconductormemory according to the fourth embodiment.

FIG. 33 is a command sequence of a read operation of a logical firstpage in the semiconductor memory according to the fourth embodiment.

FIG. 34 is a flowchart showing a write operation of the semiconductormemory according to the fourth embodiment.

FIG. 35 is a flowchart showing a write operation of the semiconductormemory according to the fourth embodiment.

FIG. 36 is a command sequence of a full sequence write operation in thesemiconductor memory according to the fourth embodiment.

FIG. 37 is a block diagram of a sense amplifier and a page bufferincluded in a semiconductor memory according to a fifth embodiment.

FIG. 38 is a diagram showing a relationship between threshold voltagedistributions and data allocations of memory cell transistors in thesemiconductor memory according to the fifth embodiment.

FIG. 39 is a diagram explaining a flow of a conversion operation of alogical page address and a physical page address in the semiconductormemory according to the fifth embodiment.

FIG. 40 is a diagram showing a logical page data allocation with respectto a physical page in the semiconductor memory according to the fifthembodiment.

FIG. 41 is a flowchart showing a read operation of the semiconductormemory according to the fifth embodiment.

FIG. 42 is a flowchart showing a read operation of the semiconductormemory according to the fifth embodiment.

FIG. 43 is a flowchart showing a read operation of the semiconductormemory according to the fifth embodiment.

FIG. 44 is a command sequence of a read operation of a logical firstpage in the semiconductor memory according to the fifth embodiment.

FIG. 45 is a command sequence of a read operation of a logical secondpage in the semiconductor memory according to the fifth embodiment.

FIG. 46 is a command sequence of a read operation of a logical thirdpage in the semiconductor memory according to the fifth embodiment.

FIG. 47 is a flow chart showing a write operation of the semiconductormemory according to the fifth embodiment.

FIG. 48 is a flow chart showing a write operation of the semiconductormemory according to the fifth embodiment.

FIG. 49 is a flow chart showing a write operation of the semiconductormemory according to the fifth embodiment.

FIG. 50 is a command sequence of a full sequence write operation in thesemiconductor memory according to the fifth embodiment.

FIG. 51 is a table showing data allocations to each state in asemiconductor memory according to a first example of a sixth embodiment.

FIG. 52 is a table showing data allocations to each state in asemiconductor memory according to a second example of the sixthembodiment.

FIG. 53 is a table showing data allocations to each state in asemiconductor memory according to a third example of the sixthembodiment.

FIG. 54 is a table showing data allocations to each state in asemiconductor memory according to a fourth example of the sixthembodiment.

FIG. 55 is a table showing data allocations to each state in asemiconductor memory according to a fifth example of the sixthembodiment.

FIG. 56 is a table showing data allocations to each state in asemiconductor memory according to a sixth example of the sixthembodiment.

FIG. 57 is a table showing data allocations to each state in asemiconductor memory according to a seventh example of the sixthembodiment.

FIG. 58 is a table showing data allocations to each state in asemiconductor memory according to an eighth example of the sixthembodiment.

FIG. 59 is a table showing data allocations to each state in asemiconductor memory according to a ninth example of the sixthembodiment.

FIG. 60 is a table showing data allocations to each state in asemiconductor memory according to a tenth example of the sixthembodiment.

FIG. 61 is a table showing data allocations to each state in asemiconductor memory according to an eleventh example of the sixthembodiment.

FIG. 62 is a table showing data allocations to each state in asemiconductor memory according to a twelfth example of the sixthembodiment.

FIG. 63 is a command sequence of a read operation of a logical firstpage in a semiconductor memory according to a first example of a seventhembodiment.

FIG. 64 is a command sequence of a read operation of a logical secondpage in the semiconductor memory according to the first example of theseventh embodiment.

FIG. 65 is a command sequence of a read operation of a logical thirdpage in the semiconductor memory according to the first example of theseventh embodiment.

FIG. 66 is a command sequence of a sequential read operation in asemiconductor memory according to a second example of the seventhembodiment.

FIG. 67 is a diagram explaining a flow of a conversion operation of alogical page address and a physical page address in a semiconductormemory according to an eighth embodiment.

FIG. 68 is a diagram showing a logical page data allocation with respectto a physical page in the semiconductor memory according to the eighthembodiment.

FIG. 69 is a block diagram of a sense amplifier and a page bufferincluded in a semiconductor memory according to a first example of aninth embodiment.

FIG. 70 is a block diagram of a sense amplifier and a page bufferincluded in a semiconductor memory according to a second example of theninth embodiment.

FIG. 71 is a block diagram of a sense amplifier and a page bufferincluded in a semiconductor memory according to a third example of theninth embodiment.

FIG. 72 is a diagram showing a logical page data allocation with respectto a physical page in a semiconductor memory according to a tenthembodiment.

FIG. 73 is a table showing data allocations to each state in thesemiconductor memory according to the tenth embodiment.

FIG. 74 is a diagram showing a logical page data allocation with respectto a physical page in a semiconductor memory according to a firstexample of an eleventh embodiment.

FIG. 75 is a diagram showing a relationship between threshold voltagedistributions and data allocations of memory cell transistors in asemiconductor memory according to a second example of the eleventhembodiment.

FIG. 76 is a diagram showing a logical page data allocation with respectto a physical page in the semiconductor memory according to the secondexample of the eleventh embodiment.

FIG. 77 is a diagram showing a relationship between threshold voltagedistributions and data allocations of memory cell transistors in asemiconductor memory according to a third example of the eleventhembodiment.

FIG. 78 is a diagram showing a logical page data allocation with respectto a physical page in the semiconductor memory according to the thirdexample of the eleventh embodiment.

FIG. 79 is a diagram showing a logical page data allocation with respectto a physical page in a semiconductor memory according to a twelfthembodiment.

FIG. 80 is a table showing data allocations to each state in thesemiconductor memory according to the twelfth embodiment.

FIG. 81 is a diagram showing threshold voltage distributions of memorycell transistors in a semiconductor memory according to a thirteenthembodiment.

FIG. 82 is a table showing data allocations by two memory celltransistors in the semiconductor memory according to the thirteenthembodiment.

FIG. 83 is a diagram showing a relationship between data allocations toan A cell and a B cell and bit values of a section in the semiconductormemory according to the thirteenth embodiment.

FIG. 84 is a diagram explaining a flow of a conversion operation of alogical page address and a physical page address in the semiconductormemory according to the thirteenth embodiment.

FIG. 85 is a diagram showing a logical page data allocation with respectto a physical page in the semiconductor memory according to thethirteenth embodiment.

FIG. 86 is a flowchart showing a read operation of the semiconductormemory according to the thirteenth embodiment.

FIG. 87 is a flowchart showing a read operation of the semiconductormemory according to the thirteenth embodiment.

FIG. 88 is a command sequence of a read operation of a logical firstpage in the semiconductor memory according to the thirteenth embodiment.

FIG. 89 is a flow chart showing a write operation of the semiconductormemory according to the thirteenth embodiment.

FIG. 90 is a flow chart showing a write operation of the semiconductormemory according to the thirteenth embodiment.

FIG. 91 is a command sequence of a full sequence write operation in thesemiconductor memory according to the thirteenth embodiment.

FIG. 92 is a diagram showing a relationship between write operations andthreshold voltage distributions of memory cell transistors in asemiconductor memory according to a modification.

DETAILED DESCRIPTION

In general, according to one embodiment, a semiconductor memoryincludes: a memory group including a plurality of memory cellsconfigured to store a plurality of bits of data in three or moreplurality of states; a word line coupled to the plurality of memorycells; and a first circuit configured to convert one external addressreceived from an external controller into a plurality of internaladdresses, wherein a first page size of page data of the memory group issmaller than a second page size of input data corresponding to theexternal address.

Hereinafter, the embodiments will be described with reference to theaccompanying drawings. In the descriptions below, constituent elementshaving similar functions and configurations will be denoted by the samereference symbols. The embodiments to be described below are shown as anexample of a device or a method for embodying the technical idea of theembodiments, and are not intended to limit the material, shape,structure, arrangement, etc. of components to those described below. Thetechnical ideas of the embodiments may be variously modified within thescope of the claims.

1. First Embodiment

A memory system according to a first embodiment will be described. Inthe following, a NAND flash memory will be given as an example of asemiconductor memory included in the memory system.

1.1 Configuration

1.1.1 Overall Configuration of Memory System

First, an overall configuration of a memory system comprising asemiconductor memory according to the present embodiment will bedescribed with reference to FIG. 1. FIG. 1 is a block diagram showing anexample of the overall configuration of the memory system. It should benoted that the configuration of a memory controller shown in FIG. 1 isan example, and therefore may take other various forms derivedtherefrom, such as an inner bus being in a divided structure or ahierarchical structure, or an additional function block being connectedthereto. A memory system 1 communicates with a host device 2, and holdsdata from the host device 2 or outputs data to the host device 2 basedon an instruction (order) from the host device 2. The host device 2 is,for example, a server computer or a personal computer, and executesinformation processing and stores data using the memory system 1. Thememory system 1 may function as a storage of the host device 2 thatfunctions as an information processing device. The memory system 1 maybe built in the host device 2, or may be coupled to the host device 2through a cable or a network. Furthermore, an information processingsystem that comprises the memory system 1 and the host device 2 may alsobe configured.

As shown in FIG. 1, the memory system 1 includes a NAND flash memory 100(hereinafter simply referred to as a “memory 100”) used as asemiconductor memory and a memory controller (also referred to as an“external controller”) 200. The memory controller 200 and the memory 100in combination, for example, may form a semiconductor storage device,and examples of such a semiconductor storage device include a memorycard, such as an SD™ card, and a solid-state drive (SSD), etc.

The memory 100 is a nonvolatile memory that includes a plurality ofmemory cell transistors (hereinafter referred to as a “memory cell” or,simply, a “cell”) and is configured to store data in a nonvolatilemanner. The memory 100 may also be configured by a plurality of NANDflash memories. In this case, the plurality of NAND flash memories inthe memory 100 may be coupled to the memory controller 200 through athrough silicon via (TSV). The NAND flash memory may be athree-dimensionally arranged NAND flash memory, in which memory celltransistors are three-dimensionally stacked above a semiconductorsubstrate, or may be a planar NAND flash memory, in which memory celltransistors are two-dimensionally arranged above the semiconductorsubstrate.

The memory 100 is coupled to the memory controller 200 via memory busesand operates based on an order from the memory controller 200. Morespecifically, the memory 100 transmits and receives, for example,signals DQ [7:0] of eight bits, and clock signals DQS and DQSn to andfrom the memory controller 200. The signals DQ [7:0] include, forexample, data, an address, and a command. The clock signals DQS and DQSnare clock signals used when inputting or outputting signals DQ, and theclock signal DQSn is an inversion signal of the clock signal DQS.

The memory 100 receives from the memory controller 200, for example, achip enable signal CEn, a command latch enable signal CLE, an addresslatch enable signal ALE, a write enable signal WEn, and a read enablesignal REn. The memory 100 transmits a ready/busy signal RBn to thememory controller 200.

The chip enable signal CEn is a signal for enabling the memory 100, andis asserted, for example, at a low (“L”) level. The command latch enablesignal CLE is a signal indicating that the signal DQ is a command, andis asserted, for example, at a high (“H”) level.

The address latch enable signal ALE is a signal indicating that thesignal DQ is an address, and is asserted, for example, at an “H” level.

The write enable signal WEn is a signal for taking a received signalinto the memory 100, and is asserted, for example, at an “L” levelwhenever a command, an address, data, or the like is received from thememory controller 200. Accordingly, whenever the write enable signal WEnis toggled, the signal DQ is taken into the memory 100.

The read enable signal REn is a signal for the memory controller 200 toread data from the memory 100. The read enable signal REn is asserted,for example, at the “L” level.

The ready/busy signal RBn is a signal indicating whether the memory 100is in a state where the signal DQ can be received from the memorycontroller 200 or in a state where the signal DQ cannot be receivedtherefrom, and is brought to the “L” level when the memory 100 is in thebusy state, for example.

The memory controller 200 instructs the memory 100 to perform a readoperation, a write operation, and an erase operation, etc., in responseto a request (order) from the host device 2. The memory controller 200also manages the memory space (memory area) of the memory 100.

The memory controller 200 includes a host interface circuit 210, anembedded memory (Random Access Memory; RAM) 220, a processor 230, abuffer memory 240, a memory interface circuit 250, and an ECC (ErrorChecking and Correcting) circuit 260. It should be noted that thefunctions of the memory controller 200 may be implemented by dedicatedcircuits, or execution of firmware by a processor.

The host interface circuit 210 is coupled to the host device 2 via ahost bus and manages communications with the host device 2. The hostinterface circuit 210 transfers a request and data received from thehost device 2 to the processor 230 and the buffer memory 240.Hereinafter, data received from the host device 2 will be referred to as“user data”. In response to an order from the processor 230, the hostinterface circuit 210 transfers the user data in the buffer memory 240to the host device 2.

The RAM 220 is, for example, a volatile memory, such as a DRAM, and isused as a work area of the processor 230. The RAM 220 holds firmware formanaging the memory 100 and various management tables, etc. The RAM 220also temporarily stores a lookup table described later.

The processor 230 controls the operation of the entire memory controller200. For example, the processor is a central processing unit (CPU) or amicro processing unit (MPU). In the case of receiving a request from thehost device 2, the processor 230 performs control in accordance with therequest For example, upon receipt of a write request (including acommand, a logical address, and user data) from the host device 2, theprocessor 230 causes the memory 100 to execute the write operation viathe memory interface circuit 250. In addition, upon receipt of a readrequest (including a command and the logical address) from the hostdevice 2, the processor 230 causes the memory 100 to execute the readoperation via the memory interface circuit 250.

The processor 230 executes various processing, such as wear leveling,for managing the memory 100. The processor 230 also executes variousarithmetic operations. For example, the processor 230 executes dataencryption processing, randomization processing, and the like.

Furthermore, the processor 230 determines a storage area (memory area)in the memory 100 for the logical address and user data received fromthe host device 2.

More specifically, for example, in the case where the processor 230receives a write request from the host device 2, the processor 230 readsdata (hereinafter referred to as a “lookup table”) associating a logicaladdress and a logical page address (also referred to as an externaladdress) from the memory 100. The logical address is attached to anaccess request from the host device 2. The logical page is a unit ofdata (input data to the memory 100) attached to an address transmittedto the memory 100 when the processor 230 controls the write operationand the read operation for the memory 100. The page size (also referredto as a “data length” or a “data amount”) of the logical pagecorresponds to the size of the user data attached to the logicaladdress. Hereinafter, the address to which the logical page is attachedwill be referred to as a “logical page address” (or, referred to as an“external address” since it is an address input to the memory 100 fromoutside). In the present embodiment, the logical page is different fromthe units of pages to be written collectively (hereinafter referred toas a “physical page”) in the memory 100. The relationship between thelogical page and the physical page will be described later. The logicalpage address corresponds to a logical page, and designates a certainpart in the memory area of the memory 100. For example, the size of alogical memory area configured by a plurality of logical pages is thesame as the size of a memory area of the memory 100 configured by aphysical page.

When a write request is received from the host device 2, the processor230 updates the lookup table in the memory controller 200 and allocatesa logical page address for a logical address. After newly allocating thelogical page address, the processor 230 causes the memory 100 to executethe write operation. Furthermore, the processor 230 updates the lookuptable in the memory 100 at a freely selected timing.

Furthermore, when a read request is received from the host device 2, forexample, the processor 230 causes the memory 100 to execute the readoperation after converting the logical address to the logical pageaddress by using the lookup table.

The buffer memory 240 temporarily stores user data received from thehost device 2 and read data received by the memory controller 200 fromthe memory 100.

The memory interface circuit 250 is coupled to the memory 100 via amemory bus, and manages communications with the memory 100. The memoryinterface circuit 250 controls the write operation, the read operation,and the erase operation, etc. in the memory 100 based on the control ofthe processor 230.

The ECC circuit 260 encodes the user data and generates a code word. Theuser data is stored in the memory 100 as an encoded code word. The ECCcircuit 260 also decodes the code word read from the memory 100.

It should be noted that the memory controller 200 does not have toencode the user data. In the case where the memory controller 200 doesnot perform coding, data to be written in the memory 100 coincides withthe user data. Furthermore, the ECC circuit 260 may generate a code wordbased on the user data corresponding to a logical page, or may generatea code word based on divided data obtained by dividing the user data.Furthermore, the ECC circuit 260 may generate a code word by using theuser data corresponding to a plurality of logical pages.

Furthermore, the ECC circuit 260 may be embedded in the memory interfacecircuit 250, or may be embedded in the memory 100.

1.1.2 Configuration of NAND Flash Memory

The configuration of the memory 100 will be described with reference toFIG. 2. FIG. 2 is a block diagram showing an internal configurationexample of the memory 100 of the present embodiment. In FIG. 2, some ofthe couplings between the blocks are indicated by arrows; however, thecouplings between the blocks are not limited to those shown in FIG. 2.

As shown in FIG. 2, the memory 100 includes an input/output circuit 110,a controller 120, a memory cell array 130, a row decoder 131, a senseamplifier 132, and a page buffer 133. The memory 100 is, for example,formed on a semiconductor substrate (a silicon substrate) and providedas a chip.

The input/output circuit 110 controls input/output of signals to or fromthe memory controller 200. More specifically, the input/output circuit110 transmits signals DQ (data DAT, logical page address, and commandCMD) and various control signals (signals CEn, CLE, ALE, WEn, and REn)received from the memory controller 200 to, for example, the controller120. The input/output circuit 110 also transmits the data DAT receivedfrom the controller 120 to the memory controller 200.

The controller 120 controls the operation of the memory 100 based on acommand CMD, etc. received from the memory controller 200 via theinput/output circuit 110. Specifically, in the case of receiving a writeorder, the controller 120 performs control to write the received writedata DAT in a physical page of the memory cell array 130. Furthermore,in the case of receiving a read order, the controller 120 performscontrol to read data DAT from the memory cell array 130 and output thedata DAT to the memory controller 200 via the input/output circuit 110.

The controller 120 includes a command user interface circuit 121, anoscillator 122, a sequencer 123, a voltage generating circuit 124, acolumn counter 125, and a serial access controller 126.

The command user interface circuit 121 receives the command CMD andlogical page address from the input/output circuit 110. The command userinterface circuit 121 transmits the received command CMD to thesequencer 123. Furthermore, the command user interface circuit 121converts the received logical page address into the address ADDcorresponding to the physical page (hereinafter also referred to as a“physical page address” or an “inner address”), and transmits it to thesequencer 123. In the present embodiment, since the page size of thelogical page is larger than the page size of the physical page, aplurality of physical pages are allocated to the logical page data ofone page. Therefore, the command user interface circuit 121 converts onelogical page address into a plurality of corresponding physical pageaddresses ADD, and transmits them to the sequencer 123. It should benoted that the logical page address may be converted into the physicalpage addresses ADD by the sequencer 123.

The oscillator 122 is a circuit for generating a clock signal. The clocksignal generated by the oscillator 122 is supplied to each componentincluding the sequencer 123. The sequencer 123 is a state machine thatis driven by the clock signal supplied from the oscillator 122.

The sequencer 123 controls an operation of the entire memory 100. Forexample, the sequencer 123 controls the command user interface circuit121, the oscillator 122, the voltage generating circuit 124, the columncounter 125, and the serial access controller 126 as well as the rowdecoder 131, the sense amplifier 132, and the page buffer 133. Thesequencer 123 controls access (the write operation, the read operation,and the erase operation) to the memory cell array 130. For example, thesequencer 123 transmits a control signal for controlling an operationtiming, etc. to the voltage generating circuit 124 and the columncounter 125 in accordance with the command CMD received from the commanduser interface circuit 121. Furthermore, the sequencer 123 supplies arow address RA included in the physical page address ADD received fromthe command user interface circuit 121 to the row decoder 131. The rowaddress RA is an address for selecting an interconnect (a word line,etc.) aligned in a row direction in the memory cell array 130.Furthermore, the sequencer 123 supplies a column address CA included inthe physical page address ADD received from the command user interfacecircuit 121 to the column counter 125. The column address CA is anaddress for selecting an interconnect (bit line, etc.) aligned in acolumn direction in the memory cell array 130.

The voltage generating circuit 124 generates voltages based on thecontrol of the sequencer 123, and supplies the voltages to the rowdecoder 131 and the sense amplifier 132, etc.

The column counter 125 transmits the column address CA to the pagebuffer 133 when performing the write operation or the read operation.Starting with the column address CA supplied from the sequencer 123 atthe head, the column counter 125 sequentially increments the columnaddress CA in accordance with a control signal supplied by the serialaccess controller 126.

The serial access controller 126 controls transmission and reception ofthe data DAT to and from the page buffer 133. More specifically, theserial access controller 126 is coupled to the page buffer 133 via adata bus. When performing the write operation, the serial accesscontroller 126 transmits the data DAT (for example, eight-bit serialdata corresponding to an eight-bit signal DQ) received from theinput/output circuit 110 to the page buffer 133. Furthermore, whenperforming the read operation, the serial access controller 126transmits the data DAT (serial data) received from the page buffer 133to the input/output circuit 110.

The memory cell array 130 includes a plurality of blocks BLK (BLK0,BLK1, . . . ) each including nonvolatile memory cell transistors(hereinafter also referred to as “memory cells”) associated with rowsand columns. Each block BLK includes a plurality of string units SU. Inthe example of FIG. 2, each block BLK includes four string units SU0,SU1, SU2, and SU3. Each string unit SU includes a plurality of NANDstrings NS. The number of blocks BLK in the memory cell array 130 andthe number of string units SU in each block BLK may be designed to beany number. The memory cell array 130 will be described in detail later.

The row decoder 131 is coupled to interconnects arranged along a rowdirection (for example, word lines and select gate lines) in each blockBLK. When performing the write operation, the read operation, and theerase operation, the row decoder 131 decodes the row address RA andapplies voltages to interconnects of a selected block ELK.

When performing the write operation, the sense amplifier 132 transfersdata stored in the page buffer 133 to the memory cell transistors.Furthermore, when performing the read operation, the sense amplifier 132determines whether the data read from the memory cell array 130 is “0”or “1”. The sense amplifier 132 transfers the obtained data to the pagebuffer 133. The data stored in the page buffer 133 is output to thememory controller 200 via the serial access controller 126 and theinput/output circuit 110.

The page buffer 133 is a buffer for temporarily storing data DATreceived from the memory controller 200 and temporarily storing dataread from the memory cell array 130. The page buffer 133 includes aplurality of latch circuits. When performing the write operation, thepage buffer 133 sequentially stores the data DAT received from theserial access controller 126 in the latch circuit corresponding to thecolumn address CA received from the column counter 125. Furthermore,when performing the read operation, the page buffer 133 sequentiallytransmits data stored in the latch circuit corresponding to the columnaddress CA received from the column counter 125 to the serial accesscontroller 126.

Hereinafter, circuits (the controller 120, the row decoder 131, thesense amplifier 132, and the page buffer 133, etc.) other than thememory cell array 130 will collectively be referred to as “peripheralcircuits”.

1.1.3 Circuit Configuration of Memory Cell Array

An example of a circuit configuration of the memory cell array 130 willbe described with reference to FIG. 3. The example of FIG. 3 shows oneblock BLK extracted from among a plurality of blocks BLK included in thememory cell array 130.

As shown in FIG. 3, for example, the block BLK includes four stringunits SU0 to SU3. Each of the string units SU includes a plurality ofNAND strings NS.

A plurality of NAND strings NS are respectively associated with bitlines BL0 to BL (k−1) (k is an integer equal to or greater than two).Each NAND string NS includes, for example, memory cell transistors MC0to MC7 and selection transistors ST1 and ST2. Hereinafter, bit lines BL0to BL (k−1) will each be simply referred to as a “bit line BL” unlessotherwise specified. Memory cell transistors MC0 to MC7 will each besimply referred to as a “memory cell transistor MC” unless otherwisespecified.

Each memory cell transistor MC includes a control gate and a chargestorage layer, and stores data in a nonvolatile manner. Each selectiontransistor ST1 and ST2 is used to select a string unit SU at the time ofperforming various operations.

Each memory cell transistor MC may be of ametal-oxide-nitride-oxide-silicon (MONOS) type that uses an insulatinglayer as the charge storage layer, or may be of a floating gate (FG)type that uses a conductive layer as the charge storage layer. In thepresent embodiment, a MONOS-type will be described as an example.

In each NAND string NS, a drain of selection transistor ST1 is coupledto an associated bit line BL, and a source of selection transistor ST1is coupled to one end of memory cell transistors MC0 to MC7, which arecoupled in series. Gates of selection transistors ST1 respectivelyincluded in string units SU0 to SU3 in the same block BLK arerespectively coupled in common to select gate lines SGD0 to SGD3. Selectgate lines SGD0 to SGD3 are coupled to the row decoder 131.

In each NAND string NS, a drain of selection transistor ST2 is coupledto the other end of memory cell transistors MC0 to MC7, which arecoupled in series. In the same block BLK, sources of selectiontransistors ST2 are coupled in common to a source line SL, and gates ofselection transistors ST2 are coupled in common to a select gate lineSGS. The select gate line SGS is coupled to the row decoder 131.

Each bit line BL commonly couples NAND strings NS that are each includedin string units SU0 to SU3 in each block BLK. The source line SL is, forexample, coupled in common among a plurality of blocks BLK.

Hereinafter, a group of a plurality of memory cell transistors MCcoupled to a common word line WL in a string unit SU will be referred toas a “memory group MG”. Each of the memory cell transistors MC includedin each memory group MG is associated respectively with bit lines BL0 toBL (k−1). Therefore, the number of memory cell transistors MC includedin a single memory group MG is k pieces. For example, the storagecapacity of a memory group MG including k pieces of memory celltransistors MC, which individually store 1-bit data, is defined asone-page data (page size) in a physical page. A memory group MG may havea storage capacity of two or more pages of data in the physical pageaccording to the number of bits of data stored in the memory celltransistor MC. Hereinafter, in the present embodiment, a case in whicheach memory cell transistor MC is capable of storing 3-bit data, thatis, a case in which the memory group MG has the storage capacity ofthree-page data in the physical pages, will be described.

The circuit configuration of the memory cell array 130 is not limited tothat described above. For example, the number of the memory celltransistors MC and the number of the selection transistors ST1 and ST2included in each NAND string NS may be determined as appropriate. Thenumber of string units SU included in each block BLK may be determinedas appropriate.

1.1.4 Cross-Sectional Configuration of Memory Cell Array

A cross-sectional configuration of the memory cell array 130 will bedescribed with reference to FIG. 4. The example of FIG. 4 shows a crosssection of a single NAND string NS. In order to simplify thedescription, in the example of FIG. 4, one transistor to be used for thesense amplifier 132 is disposed on a semiconductor substrate 30.Furthermore, in the example of FIG. 4, some of the interlayer insulatingfilms are omitted.

As shown in FIG. 4, a transistor to be used for the sense amplifier 132is provided on the semiconductor substrate 30. That is, the senseamplifier 132 is provided between the semiconductor substrate 30 and thememory cell array 130. It should be noted that other peripheralcircuits, such as the row decoder 131 or the page buffer 133, may alsobe provided between the semiconductor substrate 30 and memory cell array130. A configuration in which peripheral circuits are provided below thememory cell array 130 is also referred to as a CMOS under allay (CUA)structure. In the present embodiment, a case in which the senseamplifier 132 and the page buffer 133 are provided between thesemiconductor substrate 30 and the memory cell array 130 in a CUAstructure will be described. The memory 100 may also have a structure inwhich an array chip on which the memory cell array 130 is provided and acircuit chip on which a peripheral circuit is provided are bonded.

A configuration of the memory cell array 130 will first be described. Aninterconnect layer 32 extending in each of an X direction that isapproximately parallel to the semiconductor substrate 30 and a Ydirection that intersects the X direction, and functioning as a sourceline SL, is formed. The interconnect layer 32 is configured by aconductive material including, for example, a semiconductor material towhich an impurity is added, or a metal material.

For example, ten interconnect layers 33 respectively functioning as theselect gate line SGS, word lines WL0 to WL7, and the select gate lineSGD, and extending in the X direction are sequentially provided abovethe interconnect layer 32 in a manner spaced apart almost perpendicularto the semiconductor substrate 30 in a Z direction, with an interlayerinsulating film (not shown) interposed therebetween.

The interconnect layers 33 are configured by a conductive materialincluding, for example, a semiconductor material to which an impurity isadded, or a metal material. The interconnect layers 33 are configuredusing, for example, a stacked structure of titanium nitride(TiN)/tungsten (W) TiN functions as a barrier layer for preventing areaction between W and SiO₂ and as an adhesive layer for improvingadhesion of W when forming a layer of W by, for example, chemical vapordeposition (CVD).

A memory pillar MP is formed in a manner to penetrate the teninterconnect layers 33 and reach the interconnect layer 32 at its bottomsurface. One memory pillar MP corresponds to one NAND string NS. Thememory pillar MP includes a block insulating film 34, a charge storagelayer 35, a tunnel insulating film 36, a semiconductor layer 37, a corelayer 38, and a cap layer 39.

More specifically, a hole corresponding to the memory pillar MP isformed in a manner to penetrate the interconnect layers 33 and reach theinterconnect layer 32 at its bottom surface. The block insulating film34, the charge storage layer 35, and the tunnel insulating film 36 aresequentially stacked on a side surface of the hole. The semiconductorlayer 37 is formed in such a manner that its side surface is in contactwith the tunnel insulating film 36 and its bottom surface is in contactwith the interconnect layer 32. The semiconductor layer 37 is an area inwhich channels of the memory cell transistors MC and the selectiontransistors ST1 and ST2 are to be formed. Accordingly, the semiconductorlayer 37 functions as a signal line that couples current paths ofselection transistor ST2, memory cell transistors MC0 to MC7, and selecttransistor ST1. A core layer 38 is provided in the semiconductor layer37. A cap layer 39 is formed on the semiconductor layer 37 and the corelayer 38, in such a manner that its side surface is in contact with thetunnel insulating film 36.

For the block insulating film 34, the tunnel insulating film 36, and thecore layer 38, SiO2 is used, for example. For the charge storage layer35, for example, silicon nitride (SiN) is used. For the semiconductorlayer 37 and the cap layer 39, for example, polysilicon is used.

A contact plug 40 is formed on the cap layer 39. An interconnect layer41 that functions as a bit line BL and that extends in the Y directionis formed on the contact plug 40. The contact plug 40 and theinterconnect layer 41 are configured by a conductive material including,for example, a stacked structure of titanium (Ti)/TiN/W, or copper (Cu)

In the example of FIG. 4, one interconnect layer 33 functioning as theselect gate line SGD and one interconnect layer 33 functioning as theselect gate line SGS are provided, but a plurality of them may beprovided.

Each of the memory cell transistors MC0 to MC7 is configured by thememory pillar MP and eight interconnect layers 33 that respectivelyfunction as word lines WL0 to WL7. Similarly, each of the selectiontransistors ST1 and ST2 is configured by the memory pillar MP and twointerconnect layers 33 that respectively function as select gate linesSGD and SGS.

A transistor included in the sense amplifier 132 will be brieflydescribed.

On the semiconductor substrate 30, for example, a transistor included inthe sense amplifier 132 is provided. For example, two interconnectlayers 53 and 55 are coupled onto the source and drain of the transistorvia contact plugs 51 and 54. The interconnect layer 53 is coupled to agate electrode 52 of the transistor via the contact plug 51.

A contact plug 56 whose upper surface height is above the highestinterconnect layer 33 is formed on the interconnect layer 55corresponding to either the source or the drain of the transistor. Thecontact plug 56 is not electrically coupled to the interconnect layers32 and 33. A contact plug 57 is formed on the contact plug 56. Thecontact plug 56 is coupled to the interconnect layer 41 via the contactplug 57. The contact plugs 51, 54, 56, and 57, the gate electrode 52,and the interconnect layers 53 and 55 are configured by a conductivematerial.

1.1.5 Configurations of Sense Amplifier and Page Buffer

An example of configurations of the sense amplifier 132 and the pagebuffer 133 will be described with reference to

FIGS. 5 and 6. FIG. 5 is a block diagram of the sense amplifier 132 andthe page buffer 133. FIG. 6 is a perspective view of a CUA structure.

As shown in FIG. 5, in the present embodiment, the sequencer 123controls a plurality of memory cell transistors MC in one memory groupMG by dividing them into two areas of a first cell area and a secondcell area. Similarly, the sequencer 123 controls the sense amplifier 132and the page buffer 133 by dividing them in two in accordance with thefirst cell area and the second cell area. For example, the memory celltransistors MC included in the first cell area are associated with bitlines BL0 to BL (i−1) (i is an integer equal to or greater than 1 andsmaller than k). The memory cell transistors MC included in the secondcell area are associated with bit lines BL (i) to BL (k−1). It should benoted that the number of memory cell transistors MC included in thefirst cell area and the number of memory cell transistors MC included inthe second cell area are preferably the same. For example, in the casewhere the number of memory cell transistors MC included in the firstcell area and the number of memory cell transistors MC included in thesecond cell area are the same, a relationship such as i=k/2 will beestablished between “i” and “k”.

The sense amplifier 132 includes a plurality of sense circuits SAprovided for each bit line BL. In the read operation, the sense circuitSA reads data from the memory cell transistor MC coupled to acorresponding bit line BL, and determines whether the data is “0” or“1”. In the write operation, the sense circuit SA applies a voltage tothe bit line BL based on write data. The sense circuit SA may include alatch circuit for temporarily storing the read data or the write data.Hereinafter, a sense circuit coupled to a bit line BL corresponding tothe memory cell transistor MC included in the first cell area will bereferred to as “sense circuit SA1” Furthermore, a sense circuit coupledto a bit line BL corresponding to the memory cell transistor MC includedin the second cell area will be referred to as “sense circuit SA2”.

The page buffer 133 includes latch circuits ADL, BDL, and XDL for eachsense circuit SA. The sense circuit SA and the latch circuits ADL, BDL,and XDL are coupled to each other. In other words, the sense circuit SAand the latch circuits ADL, BDL, and XDL are coupled to each other in amanner allowing data to be transmitted and received therebetween. Thelatch circuits ADL, BDL, and XDL temporarily store data DAT. Forexample, the read data confirmed by the sense circuit SA in the readoperation is transferred to one of the latch circuits ADL, BDL, or XDLfrom the sense circuit SA.

The latch circuit XDL is coupled to the serial access controller 126 viathe data bus, and is used for transmitting and receiving data betweenthe serial access controller 126 and the sense amplifier 132.

The configuration of the page buffer 133 is not limited thereto and maybe variously modified. For example, the number of latch circuitsincluded in each page buffer 133 may be designed based on the number ofbits of data stored in a single memory cell transistor MC.

Hereinafter, the latch circuits ADL, BDL, and XDL corresponding to sensecircuit SA1 will be referred to as “latch circuit ADL1”, “latch circuitBDL1”, and “latch circuit XDL1”. Furthermore, the latch circuits ADL,BDL, and XDL corresponding to sense circuit SA2 will be referred to as“latch circuit ADL2”, “latch circuit BDL2”, and “latch circuit XDL2”.Furthermore, a set of the sense circuit SA and the latch circuits ADL,BDL, and XDL corresponding to a single bit line BL will be referred toas a “sense amplifier unit SAU”. A set of sense circuit SA1 and latchcircuits ADL1, BDL1, and XDL1 will be referred to as “sense amplifierunit SAU1”, and a set of sense circuit SA2 and latch circuits ADL2,BDL2, and XDL2 will be referred to as “sense amplifier unit SAU2”.

In the present embodiment, a plurality of sense amplifier units SAU1corresponding to the first cell area are arranged together in one area,and a plurality of sense amplifier units SAU2 corresponding to thesecond cell area are arranged together in another area.

The relationship between the memory group MG and the sense amplifierunit SAU will be described in terms of arrangement.

As shown in FIG. 6, in the case of the CUA structure, the memory cellarray 130 is arranged above the sense amplifier 132 and the page buffer133 in the Z direction. For example, in the memory cell array 130, aplurality of memory cell transistors MC included in the memory group MGare aligned in the X direction. Furthermore, a plurality of blocks BLKare aligned in the Y direction. In the sense amplifier 132 and the pagebuffer 133, the sense circuit SA and the latch circuits ADL, BDL, andXDL are aligned in the Y direction in the sense amplifier unit SAUcorresponding to a single memory cell transistor MC. In the case whereit is difficult to arrange the sense circuit SA and the latch circuitsADL, BDL, and XDL in one stage, they may be arranged in multiple stages.

1.2 Threshold Voltage Distributions of Memory Cell Transistors

Possible threshold voltage distributions of the memory cell transistorsMC will be described with reference to FIG. 7. FIG. 7 is a diagramshowing a relationship between threshold voltage distributions and dataallocations of memory cell transistors MC. Hereinafter, in the presentembodiment, a case will be described in which each memory celltransistor MC is a triple-level cell (TLC) (or referred to as “3bit/Cell”) capable of storing eight values (three bits) of data.However, data that can be stored in the memory cell transistor MC is notlimited to eight values.

As shown in FIG. 7, the threshold voltage of each memory cell transistorMC takes a value that falls within, for example, one of eight discretedistributions. Hereinafter, the eight distributions will be respectivelyreferred to as, in ascending order of threshold voltage, an “S0” state(or also referred to as a threshold area), an “S1” state, an “S2” state,an “S3” state, an “S4” state, an “S5” state, an “S6” state, and an “S7”state.

The “S0” state corresponds to, for example, a data erase state. The “S1”to “S7” states correspond to states in which a charge is injected intothe charge storage layer and data is written. In a write operation, itis assumed that verify voltages corresponding to the respectivethreshold voltage distributions are V1 to V7. In this case, the voltagevalues establish a relationship of V1<V2<V3<V4<V5<V6<V7<Vread. In theread operation, the voltages V1 to V7 are voltages to be applied to aword line WL (hereinafter also referred to as “selected word line WL”)coupled to a memory cell transistor MC that is to be read. In the readoperation, the voltage Vread is a voltage that is applied to a word lineWL (hereinafter also referred to as “non-selected word line WL”) coupledto a memory cell transistor MC that is not to be read. The memory celltransistor MC is switched to an on state upon application of the voltageVread to its gate, regardless of data stored therein.

More specifically, a threshold voltage that falls within the “S0” stateis less than the voltage V1. A threshold voltage that falls within the“S1” state is equal to or higher than the voltage V1, and less than thevoltage V2. A threshold voltage that falls within the “S2” state isequal to or higher than the voltage V2, and less than the voltage V3. Athreshold voltage that falls within the “S3” state is equal to or higherthan the voltage V3, and less than the voltage V4. A threshold voltagethat falls within the “S4” state is equal to or higher than the voltageV4, and less than the voltage V5. A threshold voltage that falls withinthe “S5” state is equal to or higher than the voltage V5, and less thanthe voltage V6. A threshold voltage that falls within the “S6” state isequal to or higher than the voltage V6, and less than the voltage V7. Athreshold voltage that falls within the “S7” state is equal to or higherthan the voltage V7, and less than the voltage Vread.

Setting values for the verify voltages and setting values for the readvoltages corresponding to the respective states may be either identicalto or different from each other. To simplify the description, a casewill be described in which the setting values for the verify voltagesand the setting values for the read voltages are the same.

Hereinafter, read operations corresponding to the read operations of the“S1” to “S7” states will be respectively referred to as read operationsR1, R2, R3, R4, R5, R6, and R7. In read operation R1, it is determinedwhether or not the threshold voltage of the memory cell transistor MC isless than the voltage V1. In read operation R2, it is determined whetheror not the threshold voltage of the memory cell transistor MC is lessthan the voltage V2. The same applies to the subsequent read operations.In each of read operations R3 to R7, it is determined whether or not thethreshold voltage of the memory cell transistor MC is less than thevoltages V3 to V7, respectively.

Each of the memory cell transistors MC belongs to one of the eightthreshold voltage distributions, thereby taking one of the eight states.By allocating these states to “000” to “111” in binary notation, eachmemory cell transistor MC is capable of storing three bits of data. Thethree bits of data will be respectively referred to as a Lower bit, aMiddle bit, and an Upper bit. Furthermore, a group of lower bits thatare collectively written into (or read from) the memory group MG isreferred to as a “lower page”, a group of middle bits that arecollectively written into (or read from) the memory group MG is referredto as a “middle page”, and a group of upper bits that are collectivelywritten into (or read from) the memory group MG is referred to as an“upper page”.

In the example of FIG. 7, data is allocated to the “upper bit/middlebit/lower bit” of each of the memory cell transistors MC that belongs toeach of the threshold voltage distributions in the following manner.Data is allocated to each state to become a Gray code in which one bitof data changes between two adjacent states.

“S0” state: “111” data

“S1” state: “101” data

“S2” state: “001” data

“S3” state: “011” data

“S4” state: “010” data

“S5” state: “110” data

“S6” state: “100” data

“S7” state: “000” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operation R4. The middle page isdetermined by read operations R1, R3, and R6. The upper page isdetermined by read operations R2, R5, and R7. That is, the values of thelower bit, the middle bit, and the upper bit are determined by one readoperation, three read operations, and three read operations,respectively. In other words, the number of voltages which is to be theboundary for determining a bit value (hereinafter referred to as a“boundary number”) is one, three, and three for the lower bit, themiddle bit, and the upper bit, respectively. Hereinafter, such dataallocation will be referred to as “1-3-3 coding” using the boundarynumber.

In the present embodiment, when allocating data for the upper bit, themiddle bit, and the lower bit, one bit whose boundary number is one isincluded. Furthermore, the boundary number of a bit whose boundarynumber is not one is coded in a manner such that the maximum value ofthe boundary number becomes minimum. For example, in the case of a TLC,that is, 3 bit/Cell, since the overall boundary number is seven, whensharing the remaining boundary number, six, with the remaining two bits,the maximum value of the boundary number will become minimum if theboundary number of each bit is set to three.

The data allocation to the “S0” to “S7” states is not limited to the1-3-3 coding.

1.3 Conversion Operation of Logical Page Address and Physical PageAddress

An example of a conversion operation of a logical page address and aphysical page address will be explained with reference to FIGS. 8 and 9.FIG. 8 is a diagram explaining a flow of the conversion operation of thelogical page address and the physical page address. FIG. 9 is a diagramshowing a logical page data allocation with respect to a physical page.

In the present embodiment, a case of allocating input data of twological pages to three physical pages (that is, one memory group MGcapable of storing three-page data) will be described.

As shown in FIG. 8, for example, when the memory controller 200 receivesa write request from the host device 2, it allocates two logical pageaddresses “90001” and “90002” corresponding to two received logicaladdresses “00001” and “00002”. Hereinafter, the two allocated logicalpages will be referred to as a “logical first page” and a “logicalsecond page”. In the example of FIG. 8, the logical first pagecorresponds to the logical page address “90001”, and the logical secondpage corresponds to the logical page address “90002”.

When the command user interface circuit 121 receives a write orderincluding two pages of the logical page address and the logical pagefrom the memory controller 200, it converts the two pages of the logicalpage address into three pages of the physical page address in accordancewith a preset mapping. In the present embodiment, the command userinterface circuit 121 converts the logical page address of the logicalfirst page into the physical page addresses of the first cell area ofthe lower page and the middle page. In addition, the command userinterface circuit 121 converts the logical page address of the logicalsecond page into the physical page addresses of the second cell area ofthe lower page and the upper page.

The page size of one page of the logical page is larger than the pagesize of one page of the physical page. However, a data amount (datalength) of two pages of the logical page is equal to a data amount (datalength) of three pages of the physical page.

In the present embodiment, the page size of one page of the logical pagewill be referred to as “m” (“m” is a number equal to or greater thanone), and the number of logical pages to be written (that is, the numberof logical page addresses included in the order) will be referred to as“a” (“a” is an integer equal to or greater than one) Furthermore, thepage size of one page of the physical page will be referred to as “n”(“n” is a number smaller than “m”), and the number of physical pages tobe written (that is, the number of bits of data that can be stored bythe memory cell transistor MC) will be referred to as “b” (“b” is aninteger larger than “a”) One page of the physical page, that is, thepage size n of one memory group MG, may then be described by n=m×a/b.Furthermore, each of the page size of the first cell area and the secondcell area may be described by n/2. In the present embodiment, since a=2and b=3, the page size of the physical page is n=m×⅔. For example, inthe case where the page size of the logical page is 16 [kB], the pagesize of the physical page is n=16×⅔=10.67 [kB]. In this case, the numberof memory cell transistors MC that can satisfy the equation for the pagesize n=10.67 [kB] of one physical page is an integer equal boor greaterthan the integer calculated by rounding up digits after the decimalpoint of 10.67×1024. In other words, the number of memory celltransistors MC is equal to or greater than the integer calculated byrounding up digits after the decimal point of the page size of onephysical page. In the present embodiment, the page size of the physicalpage is smaller than the page size of the logical page. In such a case,if the number of string units SU inside a logical block BLK configuredby the logical page and the number of string units SU inside a physicalblock BLK (that is, the block BLK of the memory cell array 130)configured by the physical page are the same, the block size (memorycapacity) of the physical block BLK is smaller than the block size(memory capacity) of the logical block BLK. Therefore, the number ofstring units SU inside the physical block BLK may, for example, beincreased from four to six so that the memory capacity of the logicalblock BLK and the memory capacity of the physical block BLK are equal.Alternatively, the number of physical blocks BLK may be increased toexceed the number of logical blocks BLK.

For example, based on the physical page address converted at the commanduser interface circuit 121, the sequencer 123 writes the data of thelogical first page in a first cell area of the lower page and the firstand second cell areas of the middle page, and writes the data of thelogical second page in the second cell area of the lower page and thefirst and second cell areas of the upper page of one memory group MG.

The arrangement of the logical page data in one memory group MG will bedescribed in detail.

As shown in FIG. 9, data of the logical first page and data of thelogical second page are divided respectively into three pieces of afirst cluster to a third cluster from the head. For example, thesequencer 123 writes a first cluster of the logical first page in thefirst cell area of the lower page, writes a second cluster of thelogical first page in the second cell area of the middle page, andwrites a third cluster of the logical first page in the first cell areaof the middle page. Furthermore, the sequencer 123 writes a firstcluster of the logical second page in the second cell area of the lowerpage, writes a second cluster of the logical second page in the firstcell area of the upper page, and writes a third cluster of the logicalsecond page in the second cell area of the upper page.

1.4 Read Operation

The read operation will be explained. In the read operation of thepresent embodiment, when the memory 100 receives a read order based onthe logical page from the memory controller 200, the memory 100 readsdata from a plurality of physical pages corresponding thereto, andoutputs the combined pieces of read data as data of the logical page.

In the present embodiment, the read operations differ depending onwhether the logical page to be read is a logical first page or a logicalsecond page. In the case where the logical page is the logical firstpage, the physical pages to be read are the lower page (the first cellarea) and the middle page (the first cell area and the second cellarea). In this case, the memory 100 transmits (outputs) data in thefirst cell area of the lower page and data in the first cell area andthe second cell area of the middle page to the memory controller 200. Onthe other hand, in the case where the logical page is the logical secondpage, the physical pages to be read are the lower page (the second cellarea) and the upper page (the first cell area and the second cell area).In this case, the memory 100 transmits (outputs) data in the second cellarea of the lower page and data in the first cell area and the secondcell area of the upper page to the memory controller 200.

1.4.1 Flow of Read Operation

The flow of the read operation in the memory 100 will first be describedwith reference to FIGS. 10 and 11. FIGS. 10 and 11 are flowcharts of theread operation.

As shown in FIGS. 10 and 11, the memory 100 receives a read order of alogical first page or a logical second page from the memory controller200 (step S1). The command user interface circuit 121 converts thelogical page address into the physical page addresses, then, transmitsthe received command and the converted physical page addresses to thesequencer 123.

In the case where the logical page address is the logical page addressof the logical first page (step S2_Yes), the sequencer 123 firstexecutes the read operation of the lower page (step S3). Morespecifically, the sequencer 123 executes read operation R4 correspondingto read voltage V4.

The sequencer 123 determines the data of the lower page based on theresult of read operation R4 (step S4).

The sequencer 123 transfers the data of the lower page read by the sensecircuits SA1 and SA2 to the latch circuits ADL1 and the ADL2,respectively (step S5).

The sequencer 123 transfers the data in the latch circuits ADL1 (data ofthe first cluster of the logical first page) to the latch circuits XDL1(step S6).

The sequencer 123 sets a head address of the latch circuit XDL1 as thecolumn address CA in the column counter 125 (step S7). Based on thecolumn address CA incremented by the column counter 125, the serialaccess controller 126 receives data sequentially from the head addressof the latch circuit XDL1 and transfers it to the input/output circuit110. The input/output circuit 110 starts transmitting (outputting) thedata in the latch circuits XDL1 to the memory controller 200.

The sequencer 123 executes a read operation of the middle page inparallel with the data output of the latch circuits XDL1 (step S8). Morespecifically, the sequencer 123 executes read operation R1 correspondingto read voltage V1, read operation R3 corresponding to read voltage V3,and read operation R6 corresponding to read voltage V6. The order ofread operations R1, R3, and R6 may be set freely.

The sequencer 123 determines the data of the middle page based on theresult of read operations R1, R3, and R6 (step S9).

The sequencer 123 transfers the data of the middle page read by thesense circuits SA1 and SA2 to the latch circuits ADL1 and the ADL2,respectively (step S10).

The sequencer 123 transfers the data in the latch circuits ADL2 (data ofthe second cluster of the logical first page) to the latch circuits XDL2(step S11).

In the case where the data output of the latch circuits XDL1 (data ofthe first cluster of the logical first page) is not ended (step S12_No),the sequencer 123 repeats a confirmation operation of the data outputuntil the output is ended.

When the data output of the latch circuits XDL1 is ended (step S12_Yes),the sequencer 123 transfers the data in the latch circuits ADL1 (data ofthe third cluster of the logical first page) to the latch circuits XDL1(step S13). The sequencer 123 ends the read operation of the logicalfirst page when the data output of the latch circuits XDL2 (data of thesecond cluster of the logical first page) and the data output of thelatch circuits XDL1 (data of the third cluster of the logical firstpage) are ended.

In the case where the logical page address is not the logical pageaddress of the logical first page (step S2_No), that is, in the casewhere the logical page address is the logical page address of thelogical second page, the sequencer 123 first executes the read operationof the lower page (step 814) in the same manner as step S3.

The sequencer 123 determines the data of the lower page based on theresult of read operation R4 (step S15).

The sequencer 123 transfers the data of the lower page read by the sensecircuits SA1 and SA2 to the latch circuits ADL1 and the ADL2,respectively (step S16).

The sequencer 123 transfers the data in the latch circuits ADL2 (data ofthe first cluster of the logical second page) to the latch circuits XDL2(step S17).

The sequencer 123 sets a head address of the latch circuit XDL2 as thecolumn address CA in the column counter 125 (step S18). Based on thecolumn address CA incremented by the column counter 125, the serialaccess controller 126 receives data sequentially from the head addressof the latch circuit XDL2 and transfers it to the input/output circuit110. The input/output circuit 110 starts transmitting (outputting) thedata in the latch circuits XDL2 to the memory controller 200.

The sequencer 123 executes a read operation of the upper page inparallel with the data output of the latch circuits XDL2 (step S19).More specifically, the sequencer 123 executes read operation R2corresponding to read voltage V2, read operation R5 corresponding toread voltage V5, and read operation R7 corresponding to read voltage V7.The order of read operations R2, R5, and R7 may be set freely.

The sequencer 123 determines the data of the upper page based on theresult of read operations R2, R5, and R7 (step S20).

The sequencer 123 transfers the data of the upper page read by the sensecircuits SA1 and SA2 to the latch circuits ADL1 and the ADL2,respectively (step S21).

The sequencer 123 transfers the data in the latch circuits ADL1 (data ofthe second cluster of the logical second page) to the latch circuitsXDL1 (step S22).

In the case where the data output of the latch circuits XDL2 (data ofthe first cluster of the logical second page) is not ended (stepS23_No), the sequencer 123 repeats a confirmation operation of the dataoutput until the output is ended.

When the data output of the latch circuits XDL2 is ended (step S23_Yes),the sequencer 123 transfers the data in the latch circuits ADL2 (data ofthe third cluster of the logical second page) to the latch circuits XDL2(step S24). In addition, the sequencer 123 sets a head address of thelatch circuit XDL1 as the column address CA in the column counter 125.Based on the column address CA incremented by the column counter 125,the serial access controller 126 receives data sequentially from thehead address of the latch circuit XDL1 and transfers it to theinput/output circuit 110. The input/output circuit 110 startstransmitting (outputting) the data in the latch circuits XDL1 to thememory controller 200. The sequencer 123 ends the read operation of thelogical second page when the data output of the latch circuits XDL1(data of the second cluster of the logical second page) and the dataoutput of the latch circuits XDL2 (data of the third cluster of thelogical second page) are ended.

1.4.2 Voltage of Selected Word Line in Read Operation

The voltage of the selected word line in the read operation will bedescribed with reference to FIGS. 12 and 13. FIG. 12 is a timing chartshowing the voltage of the selected word line WL in the read operationof the logical first page. FIG. 13 is a timing chart showing the voltageof the selected word line WL in the read operation of the logical secondpage

As shown in FIG. 12, in order to read data of the logical first page,the sequencer 123 reads data of the lower page and data of the middlepage. That is, the sequencer 123 executes read operation R4corresponding to the lower page and read operations R1, R3, and R6corresponding to the middle page in sequence.

More specifically, at time to, the row decoder 131 applies read voltageV4 corresponding to read operation R4 to the selected word line WL.

At time t1, the row decoder 131 applies read voltage V1 corresponding toread operation R1 to the selected word line WL.

At time t2, the row decoder 131 applies read voltage V3 corresponding toread operation R3 to the selected word line WL.

At time t3, the row decoder 131 applies read voltage V6 corresponding toread operation R6 to the selected word line WL.

At time t4, the row decoder 131 applies a ground voltage VSS to theselected word line WL and ends the read voltage application.

The order in which the row decoder 131 applies the voltages V1, V3, V4,and V6 to the selected word line WL is changeable. For example, the rowdecoder 131 may apply voltages to the selected word line WL in the orderof V4, V6, V3, and V1, or in the order of V1, V3, V4, and V6. The rowdecoder 131 may also apply voltages in the order of V6, V4, V3, and V1.

As shown in FIG. 13, in order to read data of the logical second page,the sequencer 123 reads data of the lower page and data of the upperpage. That is, the sequencer 123 executes read operation R4corresponding to the lower page and read operations R2, R5, and R7corresponding to the upper page in sequence.

More specifically, at time to, the row decoder 131 applies read voltageV4 corresponding to read operation R4 to the selected word line WL.

At time t1, the row decoder 131 applies read voltage V2 corresponding toread operation R2 to the selected word line WL.

At time t2, the row decoder 131 applies read voltage V5 corresponding toread operation R5 to the selected word line WL.

At time t3, the row decoder 131 applies read voltage V7 corresponding toread operation R7 to the selected word line WL.

At time t4, the row decoder 131 applies the ground voltage VSS to theselected word line WL and ends the read voltage application.

The order in which the row decoder 131 applies the voltages V2, V4, V5,and V7 to the selected word line WL is changeable. For example, the rowdecoder 131 may apply voltages to the selected word line WL in the orderof V4, V7, V5, and V2, or in the order of V2, V4, V5, and V7. The rowdecoder 131 may also apply voltages in the order of V7, V5, V4, and V2.

1.4.3 Command Sequence of Read Operation

An example of a command sequence of the read operation will be describedwith reference to FIGS. 14 and 15. FIG. 14 shows a command sequence ofthe read operation of the logical first page. FIG. 15 shows a commandsequence of the read operation of the logical second page. In theexamples of FIGS. 14 and 15, signals CEn, CLE, ALE, WEn, and REn areomitted to simplify the description. In the following description, aready/busy signal RBn that is transmitted from the memory 100 to thememory controller 200 will be referred to as an “external RBn signal”.Furthermore, an internal signal indicating whether or not the memory 100is in a busy state inside the memory 100 will be referred to as an“internal RBn signal”. In the signal DQ, a command is expressed by around frame, an address is expressed by a square frame, and data isexpressed by a hexagonal frame. Furthermore, in a case where valid dateis stored in one of the latch circuits of the page buffer 133, the latchcircuit is expressed by a square frame with rounded corners. Inaddition, the examples of FIGS. 14 and 15 also show voltages of theselected word line WL in a case where the internal RBn signal is in thebusy state.

A command sequence in the read operation of the logical first page willfirst be explained.

As shown in FIG. 14, for example, in a case where a read target is thelogical first page, the memory controller 200 transmits a command “00h”to the memory 100 to notify the read operation. The memory controller200 then transmits a logical page address “AD-P1” of the logical firstpage. In the memory 100, the command user interface circuit 121 convertsthe received logical page address “AD-P1” into the physical pageaddresses. The memory controller 200 then transmits a command “30h” tothe memory 100 to order the read operation to be executed. The commanduser interface circuit 121 sequentially transmits the received commandand the converted physical page addresses to the sequencer 123

The sequencer 123 starts the read operation in response to the command“30h”. The sequencer 123 first sets the internal RBn signal and theexternal RBn signal to the “L” level indicating the busy state. Thesequencer 123 then executes the read operation of the lower page (readoperation R4). That is, read voltage V4 is applied to the selected wordline WL. The read result of the lower page is stored in the latchcircuits ADL1 and ADL2. The data in the latch circuits ADL1 is thentransferred to the latch circuits XDL1. When the read operation of thelower page is ended, the sequencer 123 sets the external RBn signal tothe “H” level indicating a ready state. Furthermore, when the readoperation of the lower page is ended, the sequencer 123 starts the readoperation of the middle page (read operations R1, R3, and R6). That is,read voltages V1, V3, and V6 are sequentially applied to the selectedword line WL.

When the “H” level external RBn signal is received, the memorycontroller 200 transmits signal REn (not shown) to the memory 100. Theinput/output circuit 110 starts outputting data in accordance withsignal REn. The input/output circuit 110 first outputs the data in thelatch circuits XDL1. When the read operation of the middle page is endedwhile the data in the latch circuits XDL1 is being output, the sequencer123 sets the internal RBn signal to the “H” level. The read result ofthe middle page is stored in the latch circuits ADL1 and ADL2. In thecase where the output of data in the latch circuits XDL1 is ended beforeending the read operation of the middle page, the sequencer 123 maytemporarily set the external RBn signal to the “L” level (busy state),and suspend the output of data to the memory controller 200. This allowsthe data in the second cell area of the middle page to be outputsuccessively after the data in the first cell area of the lower page isoutput.

The data in the latch circuits ADL2 is then transferred to the latchcircuits XDL2. When the output of data in the latch circuits XDL1 isended, the input/output circuit 110 subsequently starts outputting datain the latch circuits XDL2. While the data in the latch circuits XDL2 isbeing output, the data in the latch circuits ADL1 is transferred to thelatch circuits XDL1. When the output of data in the latch circuits XDL2is ended, the input/output circuit 110 subsequently executes output ofdata in the latch circuits XDL1. When the output of data in the latchcircuits XDL1 is ended, the read operation of the logical first page isended. It should be noted that the memory 100 may also set the level ofthe external RBn signal to be identical to that of the internal RBnsignal, and, after reading all of the pieces of data in the logicalfirst page, set the external RBn signal (internal RBn signal) to the “H”level and output the data.

A command sequence in the read operation of the logical second page willbe explained.

As shown in FIG. 15, for example, in a case where a read target is thelogical second page, the memory controller 200 transmits a command “00h”to the memory 100 to notify the read operation. The memory controller200 then transmits a logical page address “AD-P2” of the logical secondpage. In the memory 100, the command user interface circuit 121 convertsthe received logical page address “AD-P2” into the physical pageaddresses. The memory controller 200 then transmits a command “30h” tothe memory 100 to order the read operation to be executed. The commanduser interface circuit 121 sequentially transmits the received commandand the converted physical page addresses to the sequencer 123.

The sequencer 123 starts the read operation in response to the command“30h”. The sequencer 123 first sets the internal RBn signal and theexternal RBn signal to the “L” level indicating the busy state. Thesequencer 123 then executes the read operation of the lower page (readoperation R4). That is, read voltage V4 is applied to the selected wordline WL. The read result of the lower page is stored in the latchcircuits ADL1 and ADL2. The data in the latch circuits ADL2 is thentransferred to the latch circuits XDL2. When the read operation of thelower page is ended, the sequencer 123 sets the external RBn signal tothe “H” level indicating a ready state. Furthermore, when the readoperation of the lower page is ended, the sequencer 123 starts the readoperation of the upper page (read operations R2, R5, and R7). That is,read voltages V2, V5, and V7 are sequentially applied to the selectedword line WL.

When the “H” level external RBn signal is received, the memorycontroller 200 transmits signal REn (not shown) to the memory 100. Theinput/output circuit 110 starts outputting data in accordance withsignal REn. The input/output circuit 110 first outputs the data in thelatch circuits XDL2. When the read operation of the upper page is endedwhile the data in the latch circuits XDL2 is being output, the sequencer123 sets the internal RBn signal to the “H” level. The read result ofthe upper page is stored in the latch circuits ADL1 and ADL2. In thecase where the output of data in the latch circuits XDL2 is ended beforeending the read operation of the upper page, the sequencer 123 maytemporarily set the external RBn signal to the “L” level (busy state),and suspend the output of data to the memory controller 200. This allowsthe data in the first cell area of the upper page to be outputsuccessively after the data in the second cell area of the lower page isoutput.

The data in the latch circuits ADL1 is then transferred to the latchcircuits XDL1. When the output of data in the latch circuits XDL2 isended, the input/output circuit 110 subsequently starts outputting datain the latch circuits XDL1. While the data in the latch circuits XDL1 isbeing output, the data in the latch circuits ADL2 is transferred to thelatch circuits XDL2. When the output of data in the latch circuits XDL1is ended, the input/output circuit 110 subsequently executes output ofdata in the latch circuits XDL2. When the output of data in the latchcircuits XDL2 is ended, the read operation of the logical second page isended. It should be noted that the memory 100 may also set the level ofthe external RBn signal to be identical to that of the internal RBnsignal, and, after reading all of the pieces of data in the logicalsecond page, set the external RBn signal (internal RBn signal) to the“H” level and output the data.

1.5 Write Operation

The write operation will be described below. The write operationincludes a program operation and a program verify operation. The programoperation refers to an operation of injecting electrons into the chargestorage layer to increase a threshold voltage (or maintaining thethreshold value by hardly injecting electrons into the charge storagelayer). The program verify operation is an operation of reading dataafter the program operation and determining whether or not a thresholdvoltage of a memory cell transistor MC has reached a target level.Hereinafter, a case in which the threshold voltage of the memory celltransistor MC has reached the target level will be referred to as“verification passed”, and a case in which it has not reached the targetlevel will be referred to as “verification failed.” More specifically,for example, a case in which the number of failed bits of the read datais equal to or greater than a preset reference value in the programverify operation will be determined to be “verification failed”. Byrepeating the combination of the program operation and the programverify operation (hereinafter referred to as a “program loop”), thethreshold voltage of the memory cell transistor MC is increased to thetarget level.

In the present embodiment, the data of the logical first page and thedata of the logical second page are collectively written in the memorygroup MG including the lower page, the middle page, and the upper page.That is, three bits of data is collectively written in one memory celltransistor MC. Hereinafter, an operation of collectively writing piecesof data of a plurality of physical pages will be referred to as a “fullsequence write operation”. In the full sequence write operation of thepresent embodiment, the “S1” to “S7” states are written. For example, inthe full sequence write operation, writing is executed in ascendingorder of states with lower threshold voltages. For example, in the casewhere the page size of the logical page and the page size of thephysical page are the same, when the “S1” to “S3” states are written inthe memory cell array 130, the latch circuits XDL would not be neededfor the write operations of the “S1” to “S3” states. Therefore, thelatch circuits XDL are used as the cache memory for the next write data.However, in the case of the present embodiment, since the number ofphysical latch circuits XDL is ⅔ (for example, 10.67 kB) of the pagesize of the logical page (for example, 16 kB), the latch circuits XDLcannot store all of the pieces of data on the one page data of thelogical page. Therefore, after inputting ⅔ of the page data of thelogical page to the available latch circuits XDL, signal RBn istemporarily set to the busy state. After the “S1” to “S5” states arewritten in the memory cell array 130, and the latch circuits ADL or thelatch circuits BDL is no longer needed for the write operation, signalRBn may be set to the ready state, and the remaining page data of thelogical page may be input to the latch circuits XDL. Alternatively, alatch circuit may be added to each of the sense amplifier units SAU.

In the present embodiment, by transferring the input data alternately tothe latch circuits XDL1 and XDL2, the memory 100 controls data input ofthe logical page to be performed successively.

1.5.1 Flow of Write Operation

The flow of the write operation in the memory 100 will be described withreference to FIGS. 16 and 17. FIGS. 16 and 17 are flowcharts of thewrite operation.

As shown in FIGS. 16 and 17, when receiving the write order, the memory100 receives a logical page address of the logical first page from thememory controller 200 (step S201). The command user interface circuit121 converts the logical page address of the logical first page into thephysical page addresses.

The sequencer 123 sets a head address of the latch circuit XDL1 as thecolumn address CA in the column counter 125 (step S202)

In the page buffer 133, data input of the first cluster of the logicalfirst page to the latch circuits XDL1 is started based on the columnaddress CA received from the column counter 125 (step S203).

In the case where the data input of the first cluster of the logicalfirst page to the latch circuits XDL1 is not ended (step S204_No), thesequencer 123 repeats a confirmation operation of the data input untilthe input is ended.

When the data input to the latch circuits XDL1 is ended (step S204_Yes),the sequencer 123 transfers the data in the latch circuits XDL1 to thelatch circuits ADL1 (step S205). Furthermore, when the data input to thelatch circuits XDL1 is ended, data input of the second cluster of thelogical first page to the latch circuits XDL2 is started subsequently.It should be noted that step S205 may be executed during the data inputof the second cluster of the logical first page to the latch circuitsXDL2.

In the case where the data input of the second cluster of the logicalfirst page to the latch circuits XDL2 is not ended (step S206_No), thesequencer 123 repeats a confirmation operation of the data input untilthe input is ended.

When the data input to the latch circuits XDL2 is ended (step S206_Yes),the sequencer 123 sets a head address of the latch circuit XDL1 as thecolumn address CA in the column counter 125 (step S207).

In the page buffer 133, data input of the third cluster of the logicalfirst page to the latch circuits XDL1 is started based on the columnaddress CA received from the column counter 125.

In the case where the data input of the third cluster of the logicalfirst page to the latch circuits XDL1 is not ended (step S208_No), thesequencer 123 repeats a confirmation operation of the data input untilthe input is ended.

When the data input to the latch circuits XDL1 is ended (step S208_Yes),data input of the logical first page to the latch circuits XDL1 and XDL2is ended.

The sequencer 123 transfers the data in the latch circuits XDL1 and XDL2to the latch circuits BDL1 and BDL2, respectively (step S209).

The memory 100 then receives a logical page address of the logicalsecond page from the memory controller 200 (step S210) The command userinterface circuit 121 converts the logical page address of the logicalsecond page into the physical page addresses. It should be noted thatthe sequencer 123 may also transfer the data in the latch circuits XDL2to the latch circuits BDL2 during the data input of the third cluster ofthe logical first page to the latch circuits XDL1.

The sequencer 123 sets a head address of the latch circuit XDL2 as thecolumn address CA in the column counter 125 (step S211).

In the page buffer 133, data input of the first cluster of the logicalsecond page to the latch circuits XDL2 is started based on the columnaddress CA received from the column counter 125 (step S212). It shouldbe noted that the sequencer 123 may also transfer the data in the latchcircuits XDL1 to the latch circuits BDL1 during the data input of thefirst cluster of the logical second page to the latch circuits XDL2.

In the case where the data input of the first cluster of the logicalsecond page to the latch circuits XDL2 is not ended (step S213_No), thesequencer 123 repeats a confirmation operation of the data input untilthe input is ended.

When the data input to the latch circuits XDL2 is ended (step S213_Yes),the sequencer 123 transfers the data in the latch circuits XDL2 to thelatch circuits ADL2 (step S214). Furthermore, the sequencer 123 sets ahead address of the latch circuit XDL1 as the column address CA in thecolumn counter 125 (step S215). In the page buffer 133, data input ofthe second cluster of the logical second page to the latch circuits XDL1and data input of the third cluster of the logical second page to thelatch circuits XDL2 are sequentially executed based on the columnaddress CA received from the column counter 125. It should be notedthat, in the case of step S213_Yes, the data input of the second clusterof the logical second page to the latch circuits XDL1 may be startedsubsequently, and the sequencer 123 may execute step S214 in themeantime.

In the case where the data input of the third cluster of the logicalsecond page to the latch circuits XDL2 is not ended (step S216_No), thesequencer 123 repeats a confirmation operation of the data input untilthe input is ended.

When the data input to the latch circuits XDL2 is ended (step S216_Yes),the data input of the logical second page to the latch circuits XDL1 andXDL2 is ended. The sequencer 123 sets the external RBn signal and theinternal RBn signal to the “L” level. The sequencer 123 then determinesthe state of each of the memory cell transistors MC based on the inputdata of the logical first page and the input data of the logical secondpage, that is, the combination of data in the lower page, the middlepage, and the upper page.

The sequencer 123 executes the program operation based on the determinedstates (step S217).

After ending the program operation, the sequencer 123 performs theprogram verify operation (step S218)

In the case where the verification is not passed (step S219_No), thesequencer 123 confirms whether or not the number of program loops hasreached the preset upper limit number (step S220).

In the case where the number of program loops has not reached the upperlimit number (step S220_No), the sequencer 123 executes the programoperation (step S217). That is, the sequencer 123 repeats the programloop.

In the case where the number of program loops has reached the upperlimit number (step S220_Yes), the sequencer 123 ends the write operationand reports to the memory controller 200 that the write operation didnot end successfully.

In the case of passing the verification (step S219_Yes), that is, endingwriting of the “S1” to “S7” states, the sequencer 123 sets the externalRBn signal to the “H” level and ends the full sequence write operation.

1.5.2 Command Sequence of Write Operation

An example of a command sequence of the write operation will bedescribed with reference to FIG. 18. FIG. 18 is a command sequence of afull sequence write operation. In the example of FIG. 18, signals CEn,CLE, ALE, WEn, and REn are omitted to simplify the description.

As shown in FIG. 18, the memory controller 200 first transmits a command“80h” to the memory 100 to notify the write operation. The memorycontroller 200 then transmits a logical page address “AD-P1” of thelogical first page. In the memory 100, the command user interfacecircuit 121 converts the received logical page address “AD-P1” into thephysical page addresses. The memory controller 200 then transmits dataof the logical first page to the memory 100. The first cluster of thelogical first page is stored in the latch circuits XDL1, and is thentransferred to the latch circuits ADL1. The second cluster of thelogical first page is stored in the latch circuits XDL2, and is thentransferred to the latch circuits BDL2. The third cluster of the logicalfirst page is stored in the latch circuits XDL1, and is then transferredto the latch circuits BDL1.

The memory controller 200 then transmits a command “1Ah” to the memory100 to notify data input of the next logical page. The memory controller200 then transmits the command “80h” and a logical page address “AD-P2”of the logical second page to the memory 100. In the memory 100, thecommand user interface circuit 121 converts the received logical pageaddress “AD-P2” into the physical page addresses. The memory controller200 then transmits data of the logical second page to the memory 100.The first cluster of the logical second page is stored in the latchcircuits XDL2, and is then transferred to the latch circuits ADL2. Thesecond cluster of the logical second page is stored in the latchcircuits XDL1. The third cluster of the logical second page is stored inthe latch circuits XDL2. The memory controller 200 then transmits acommand “10h” to the memory 100 to instruct execution of the writeoperation.

When the command “10h” is received, the sequencer 123 sets the internalRBn signal and the external RBn signal to the “L” level. The sequencer123 then determines the state of each of the memory cell transistors MCbased on the data stored in the latch circuits ADL1, ADL2, BDL1, BDL2,XDL1, and XDL2, and then executes the write operation. After ending thewrite operation, the sequencer 123 sets the internal RBn signal and theexternal RBn signal to the “H” level. It should be noted that the firstcluster of the logical first page is stored in the latch circuits XDL1,and is then transferred to the latch circuits ADL1 while the data of thesecond cluster of the logical first page is being stored in the latchcircuits XDL2. The second cluster of the logical first page is stored inthe latch circuits XDL2, and is then transferred to the latch circuitsBDL2 while the data of the third cluster of the logical first page isbeing stored in the latch circuits XDL1. The third cluster of thelogical first page is stored in the latch circuits XDL1, and is thentransferred to the latch circuits BDL1 while the data of the firstcluster of the logical second page is being stored in the latch circuitsXDL2. The first cluster of the logical second page is stored in thelatch circuits XDL2, and is then transferred to the latch circuits ADL2while the data of the second cluster of the logical second page is beingstored in the latch circuits XDL1. The second cluster of the logicalsecond page is stored in the latch circuits XDL1. The third cluster ofthe logical second page is stored in the latch circuits XDL2. Thisallows the time of transferring data from the latch circuits XDL1 to thethe latch circuits ADL1 or the latch circuits BDL1 and the time oftransferring data from the latch circuits XDL2 to the latch circuitsADL2 or the latch circuits BDL2, to be invisible from the outside (thememory controller 200). Furthermore, when data input of the logicalfirst page starts from the second cluster or the third cluster of thelogical first page, data is input to the latch circuits XDL2 and XDL1 orthe latch circuits XDL1, and is then transferred to the latch circuitsBDL1 and BDL2 or the latch circuits BDL1. Furthermore, when data inputof the logical second page starts from the second cluster or the thirdcluster of the logical second page, data is input to the latch circuitsXDL1 and XDL2 or the latch circuits XDL2, and the write operation isstarted subsequently. In this case, the latch circuits XDL to which nodata is input is set to “1” (non-write data).

1.6 Advantageous Effects of First Embodiment

According to the configuration of the present embodiment, it is possibleto suppress increasing a chip area of the semiconductor memory. Theeffects will be explained in detail.

In order to increase a storage capacity of a flash memory, memory celltransistor has been miniaturized. By miniaturizing peripheral circuitssuch as sense amplifiers and page buffers with the miniaturization ofthe memory cell transistor, the chip area can be reduced, therebyincreasing capacitance density per chip area. However, theminiaturization rate of the peripheral circuits is milder than theminiaturization rate of the memory cell transistor. This is because aleak current may increase or a memory life may deteriorate if thetransistor size of the peripheral circuit is reduced before theoperation voltage can be lowered.

In order to increase the capacitance density per chip area, aconfiguration in which a peripheral circuit is provided below the memorycell array, that is, between the memory cell array and a semiconductorsubstrate, or a configuration in which a peripheral circuit is formed onanother semiconductor substrate and is bonded together with the memorycell array, etc. is proposed. In the case of such a configuration, evenif the memory cell array becomes miniaturized and highly integrated(highly laminated) and the area of the memory cell array is reduced, thearea of the peripheral circuit would not be largely reduced, which maycause the area of the peripheral circuit to become larger than the areaof the memory cell array. As a result, since the chip size is determinedby the size of the peripheral circuit, in some cases, theminiaturization and high lamination of the memory cell array may bedifficult to cause the chip area to be reduced.

In contrast, according to the configuration of the present embodiment,the page size of the physical page can be made smaller than the pagesize of the logical page. More specifically, write data in the page sizeof the logical page can be divided and written on a plurality ofphysical pages. Furthermore, pieces of data read from a plurality ofphysical pages can be combined and output as data of the logical page.Since the page size of the physical page can be reduced, the number ofsense amplifier units SAU corresponding to the physical page can bereduced. That is, the number of sense circuits inside the senseamplifier 132 and the number of latch circuits inside the page buffer133 can be reduced. Therefore, the chip area of the semiconductor memorycan be suppressed from increasing.

Furthermore, according to the configuration of the present embodiment,the page size of the physical page can be made smaller than the pagesize of the logical page, which allows the areas of the sense amplifier132 and the page buffer 133 (the number of sense circuits and the numberof latch circuits) to be reduced. Therefore, the area of the peripheralcircuit can be reduced even in the case where the area of the memorycell array 130 is reduced by the miniaturization and high lamination ofthe memory cell array 130. That is, a mismatch between the area of thememory cell array 130 and the area of the peripheral circuit providedbelow the memory cell array 130 can be reduced. Therefore, theminiaturization and high lamination of the memory cell array 130 wouldbe easily reflected in the chip area reduction.

Furthermore, according to the configuration of the present embodiment,pieces of data read from a plurality of physical pages can be combinedand output as data of the logical page. Therefore, the semiconductormemory of the present embodiment can be applied without changing thespecification of the memory controller 200. That is, the system can beeasily designed since the data management method in a memory system onwhich the semiconductor memory of the present embodiment is mounted canbe used as it is.

Furthermore, according to the configuration of the present embodiment,the page size of the physical page can be made small. That is, thenumber of memory cell transistors MC included in one memory group MGcoupled to a word line WL can be reduced. It is thereby possible toreduce the interconnect length of the word lines WL. Accordingly, theinterconnect resistance and the interconnect capacitance of the wordlines WL can be reduced. Therefore, a charge-and-discharge time of avoltage to be applied to the word lines WL can be shortened in the readoperation and the write operation. Accordingly, a processing timerequired for the read operation and the write operation can besuppressed from increasing.

Furthermore, in the configuration according to the present embodiment,one bit with the boundary number of one is included in the data codingapplied to the physical page. Furthermore, the boundary number of a bitwhose boundary number is not one is coded in a manner such that themaximum value of the boundary number becomes minimum. It is therebypossible to suppress the increase in the read time caused by theincrease in the boundary numbers (the number of read operations) in thecase of reading a plurality of physical pages corresponding to onelogical page.

2. Second Embodiment

A second embodiment will be explained. In the second embodiment, sevenexamples will be given for a TLC coding that is different from the firstembodiment. Hereinafter, the description will focus mainly on mattersdifferent from those of the first embodiment.

2.1 First Example

A first example of the coding will first be described with reference toFIG. 19. FIG. 19 is a table showing data allocations to each state.

As shown in FIG. 19, in the present embodiment, in the same manner asthe first embodiment, data is allocated to each state to become a Graycode in which one bit of data changes between two adjacent states.

“S0” state: “111” data

“S1” state: “011” data

“S2” state: “001” data

“S3” state: “101” data

“S4” state: “100” data

“S5” state: “110” data

“S6” state: “010” data

“S7” state: “000” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operation R4. The middle page isdetermined by read operations R2, R5, and R7. The upper page isdetermined by read operations R1, R3, and R6. Therefore, the dataallocation of the present example is a 1-3-3 coding as in the firstembodiment.

In the present example, in the same manner as the first embodiment, whenallocating data for the upper bit, the middle bit, and the lower bit,one bit whose boundary number is one is included. Furthermore, theboundary number of a bit whose boundary number is not one is coded in amanner such that the maximum value of the boundary number becomesminimum.

2.2 Second Example

A second example of the coding will be described with reference to FIG.20. FIG. 20 is a table showing data allocations to each state.

As shown in FIG. 20, in the present embodiment, in the same manner asthe first embodiment, data is allocated to each state to become a graycode in which one bit of data changes between two adjacent states.

“S0” state: “110” data

“91” state: “100” data

“S2” state: “000” data

“S3” state: “010” data

“S4” state: “011” data

“S5” state: “111” data

“S6” state: “101” data

“S7” state: “001” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operation R4. The middle page isdetermined by read operations R1, R3, and R6. The upper page isdetermined by read operations R2, R5, and R7. Therefore, the dataallocation of the present example is a 1-3-3 coding as in the firstembodiment.

In the present example, in the same manner as the first embodiment, whenallocating data for the upper bit, the middle bit, and the lower bit,one bit whose boundary number is one is included. Furthermore, theboundary number of a bit whose boundary number is not one is coded in amanner such that the maximum value of the boundary number becomesminimum.

2.3 Third Example

A third example of the coding will be described with reference to FIG.21. FIG. 21 is a table showing data allocations to each state.

As shown in FIG. 21, in the present embodiment, in the same manner asthe first embodiment, data is allocated to each state to become a Graycode in which one bit of data changes between two adjacent states.

“S0” state: “110” data

“S1” state: “010” data

“S2” state: “000” data

“S3” state: “100” data

“S4” state: “101” data

“S5” state: “111” data

“S6” state: “011” data

“S7” state: “001” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operation R4. The middle page isdetermined by read operations R2, R5, and R7. The upper page isdetermined by read operations R1, R3, and R6. Therefore, the dataallocation of the present example is a 1-3-3 coding as in the firstembodiment.

In the present example, in the same manner as the first embodiment, whenallocating data for the upper bit, the middle bit, and the lower bit,one bit whose boundary number is one is included. Furthermore, theboundary number of a bit whose boundary number is not one is coded in amanner such that the maximum value of the boundary number becomesminimum.

2.4 Fourth Example

A fourth example of the coding will be described with reference to FIG.22. FIG. 22 is a table showing data allocations to each state.

As shown in FIG. 22, in the present embodiment, in the same manner asthe first embodiment, data is allocated to each state to become a Graycode in which one bit of data changes between two adjacent states.

“S0” state: “111” data

“S1” state: “101” data

“S2” state: “001” data

“S3” state: “011” data

“S4” state: “010” data

“S5” state: “000” data

“S6” state: “100” data

“S7” state: “110” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operation R4. The middle page isdetermined by read operations R1, R3, R5, and R7. The upper page isdetermined by read operations R2 and R6. Therefore, the data allocationof the present example is a 1-4-2 coding.

In the present example, in the same manner as the first embodiment, whenallocating data for the upper bit, the middle bit, and the lower bit,one bit whose boundary number is one is included. However, in thepresent example, the boundary number of a bit whose boundary number isnot one is not coded in a manner such that the maximum value of theboundary number becomes minimum.

2.5 Fifth Example

A fifth example of the coding will be described with reference to FIG.23. FIG. 23 is a table showing data allocations to each state.

As shown in FIG. 23, in the present embodiment, in the same manner asthe first embodiment, data is allocated to each state to become a Graycode in which one bit of data changes between two adjacent states.

“S0” state: “111” data

“S1” state: “011” data

“S2” state: “001” data

“S3” state: “101” data

“S4” state: “100” data

“S5” state: “000” data

“S6” state: “010” data

“S7” state: “110” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operation R4. The middle page isdetermined by read operations R2 and R6. The upper page is determined byread operations R1, R3, R5, and R7. Therefore, the data allocation ofthe present example is a 1-2-4 coding.

In the present example, in the same manner as the first embodiment, whenallocating data for the upper bit, the middle bit, and the lower bit,one bit whose boundary number is one is included. However, in thepresent example, the boundary number of a bit whose boundary number isnot one is not coded in a manner such that the maximum value of theboundary number becomes minimum.

2.6 Sixth Example

A sixth example of the coding will be described with reference to FIG.24. FIG. 24 is a table showing data allocations to each state.

As shown in FIG. 24, in the present embodiment, in the same manner asthe first embodiment, data is allocated to each state to become a Graycode in which one bit of data changes between two adjacent states.

“S0” state: “110” data

“S1” state: “100” data

“S2” state: “000” data

“S3” state: “010” data

“S4” state: “011” data

“S5” state: “001” data

“S6” state: “101” data

“S7” state: “111” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operation R4. The middle page isdetermined by read operations R1, R3, R5, and R7. The upper page isdetermined by read operations R2 and R6. Therefore, the data allocationof the present example is a 1-4-2 coding.

In the present example, in the same manner as the first embodiment, whenallocating data for the upper bit, the middle bit, and the lower bit,one bit whose boundary number is one is included. However, in thepresent example, the boundary number of a bit whose boundary number isnot one is not coded in a manner such that the maximum value of theboundary number becomes minimum.

2.7 Seventh Example

A seventh example of the coding will be described with reference to FIG.25. FIG. 25 is a table showing data allocations to each state.

As shown in FIG. 25, in the present embodiment, in the same manner asthe first embodiment, data is allocated to each state to become a Graycode in which one bit of data changes between two adjacent states.

“S0” state: “110” data

“S1” state: “010” data

“S2” state: “000” data

“S3” state: “100” data

“S4” state: “101” data

“S5” state: “001” data

“S6” state: “011” data

“S7” state: “111” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operation R4. The middle page isdetermined by read operations R2 and R6. The upper page is determined byread operations R1, R3, R5, and R7. Therefore, the data allocation ofthe present example is a 1-2-4 coding.

In the present example, in the same manner as the first embodiment, whenallocating data for the upper bit, the middle bit, and the lower bit,one bit whose boundary number is one is included. However, in thepresent example, the boundary number of a bit whose boundary number isnot one is not coded in a manner such that the maximum value of theboundary number becomes minimum.

2.8 Advantageous Effects of Second Embodiment

The coding of the present embodiment is applicable to the firstembodiment.

The configuration of the present embodiment can attain the same effectas the first embodiment.

3. Third Embodiment

A third embodiment will be explained. In the third embodiment, twoexamples will be given to explain the read operation that is differentfrom that of the first embodiment. Hereinafter, the description willfocus mainly on matters different from those of the first embodiment.

3.1 First Example

A read operation of a first example will first be explained. In thefirst example, a case in which the order of the read voltages to beapplied to the selected word line WL is different from that of the firstembodiment in read operations of the logical first page and the logicalsecond page will be explained with reference to FIGS. 26 and 27. FIG. 26shows a command sequence of the read operation of the logical firstpage. FIG. 27 shows a command sequence of the read operation of thelogical second page. In the examples of FIGS. 26 and 27, signals CEn,CLE, ALE, WEn, and REn are omitted to simplify the description. Inaddition, the examples of FIGS. 26 and 27 also show voltages of theselected word line WL in a case where the internal RBn signal is in thebusy state.

The command sequence in the read operation of the logical first pagewill first be explained.

As shown in FIG. 26, in the read operation of the lower page (readoperation RA) and the read operation of the middle page (read operationsR1, R3, and R6) corresponding to the logical first page, the sequencer123 executes the read operations in the order of R6, R4, R3, and R1.That is, read voltages V6, V4, V3, and V1 are sequentially applied tothe selected word line WL. In this case, in the same manner as the firstembodiment, after read operation R4 corresponding to the lower page isended, the external RBn signal is set to the “H” level. The read resultof the lower page is then stored in latch circuits ADL1 and ADL2. Itshould be noted that the memory 100 may also set the level of theexternal RBn signal identical to that of the internal RBn signal, and,after reading all of the pieces of data in the logical first page, setthe external RBn signal (internal RBn signal) to the “H” level andoutput the data.

It should be noted that the sequencer 123 may also execute the readoperation in the order of R1, R3, R4, and R6. That is, read voltages V1,V3, V4, and V6 may be sequentially applied to the selected word line WL.

The command sequence in the read operation of the logical second pagewill be explained.

As shown in FIG. 27, in the read operation of the lower page (readoperation R4) and the read operation of the upper page (read operationsR2, R5, and R7) corresponding to the logical second page, the sequencer123 executes the read operations in the order of R7, R5, R4, and R2.That is, read voltages V7, V5, V4, and V2 are sequentially applied tothe selected word line WL. In this case, in the same manner as the firstembodiment, after read operation R4 corresponding to the lower page isended, the external RBn signal is set to the “H” level. The read resultof the lower page is then stored in latch circuits ADL1 and ADL2. Itshould be noted that the memory 100 may also set the level of theexternal RBn signal to be identical to that of the internal RBn signal,and, after reading all of the pieces of data in the logical second page,set the external RBn signal (internal RBn signal) to the “H” level andoutput the data.

It should be noted that the sequencer 123 may also execute the readoperation in the order of R2, R4, R5, and R7. That is, read voltages V2,V4, V5, and V7 may be sequentially applied to the selected word line WL.

3.2 Second Example

A read operation of a second example will be explained. In the presentexample, a case in which pieces of data of the lower page, the middlepage, and the upper page are collectively read will be explained withreference to FIG. 28. Hereinafter, such the read operation will bereferred to as a “sequential read operation”. In the sequential readoperation of the present example, the “S0” state to “S7” state arecollectively read. FIG. 28 shows a command sequence of the sequentialread operation. In the example of FIG. 28, signals CEn, CLE, ALE, WEn,and REn are omitted to simplify the description. In the example of FIG.28, some of the commands and addresses are omitted. In addition, theexample of FIG. 28 also shows voltages of the selected word line WL in acase where the internal RBn signal is in the busy state.

As shown in FIG. 28, when the sequencer 123 receives a command “30h”,the sequencer 123 starts the read operation in response to the command.The sequencer 123 first sets the internal RBn signal and the externalRBn signal to the “L” level, indicating the busy state. The sequencer123 then executes the sequential read operation. More specifically, thesequencer 123 sequentially executes read operations R1 to R7. At thistime, read voltages V1 to V7 are sequentially applied to the selectedword line WL. When read operation R4 is ended, the sequencer 123determines the data of the lower page and sets the external RBn signalto the “H” level. The data of the lower page is stored in the latchcircuits ADL1 and ADL2. Then, the data in the latch circuits ADL1 (dataof the first cluster of the logical first page) is transferred to thelatch circuits XDL1. When the “H” level external RBn signal is received,the memory controller 200 transmits signal REn (not shown) to the memory100. The input/output circuit 110 starts outputting data in accordancewith signal REn. The input/output circuit 110 first outputs the data inthe latch circuits XDL1 (the data of the first cluster of the logicalfirst page)

When read operation R6 is ended, the sequencer 123 then determines dataof the middle page. The data of the middle page is stored in the latchcircuits BDL1 and BDL2. The data in the latch circuits BDL2 (data of thesecond cluster of the logical first page) is transferred to the latchcircuits XDL2. The data in the latch circuits BDL1 (data of the thirdcluster of the logical first page) is transferred to the latch circuitsXDL1 after ending output of the data of the lower page (the data of thefirst cluster of the logical first page) stored in the latch circuitsXDL1.

When the sequential read operation is ended while the data in the latchcircuits XDL1 or XDL2 is being output, the sequencer 123 sets theinternal RBn signal to the “H” level.

When output of the data of the middle page stored in the latch circuitsXDL2 (the data of the second cluster of the logical first page) isended, the data in the latch circuits ADL2 (data of the first cluster inthe logical second page) is transferred to the latch circuits XDL2.

When output of the data of the middle page stored in the latch circuitsXDL1 (the data of the third cluster of the logical first page) is ended,the data output of the logical first page is ended, and data output ofthe logical second page is started subsequently. The data of the lowerpage stored in the latch circuits XDL2 (the data of the first cluster ofthe logical second page) is output. Furthermore, when output of the dataof the middle page stored in the latch circuits XDL1 (the data of thethird cluster of the logical first page) is ended, the data of the upperpage (the data of the second cluster of the logical second page) istransferred to the latch circuits XDL1 from the sense circuits SA1.

When output of the data of the upper page stored in the latch circuitsXDL2 (the data of the first cluster of the logical second page) isended, data of the sense circuits SA2 (data of the third cluster of thelogical second page) is transferred to the latch circuits XDL2. Whenoutput of the data in the latch circuits XDL2 (the data of the thirdcluster of the logical second page) is ended, the sequential readoperation is ended.

It should be noted that the sequencer 123 may also execute the readoperation in the order of R7 to R1. That is, voltages may be applied tothe selected word line WL in the order of voltages V7 to V1. It shouldbe noted that the memory 100 may also set the level of the external RBnsignal to be identical to that of the internal RBn signal, and, afterreading all of the pieces of data, set the external RBn signal (internalRBn signal) to the “H” level and output the data.

3.3 Advantageous Effects of Third Embodiment

The coding of the present embodiment is applicable to the firstembodiment.

The configuration of the present embodiment can attain the same effectas the first embodiment.

Furthermore, according to the configuration of the present embodiment,when performing the read operation, the read voltage can be applied inascending order or in descending order. It is thus possible to suppressthe increase in the variation range of voltages to be applied to theselected word line WL. Thus, the transition time required for thevoltages applied to the selected word line WL can be shortened, therebyreducing the processing time of the read operation.

4. Fourth Embodiment

A fourth embodiment will be described. In the fourth embodiment, a caseof allocating data of one logical page to two physical pages (that is,one memory group MG capable of storing two-page data) will be described.Hereinafter, the description will focus mainly on matters different fromthose of the first to third embodiments.

4.1 Threshold Voltage Distributions of Memory Cell Transistors

Possible threshold voltage distributions of memory cell transistors MCwill first be described with reference to FIG. 29. FIG. 29 is a diagramshowing a relationship between threshold voltage distributions and dataallocations of memory cell transistors MC. Hereinafter, in the presentembodiment, a case will be described in which each memory celltransistor MC is a multi-level cell (MLC) (or referred to as “2bit/Cell”) capable of storing four values (two bits) of data.

As shown in FIG. 29, the threshold voltage of each memory celltransistor MC takes a value that falls within, for example, one of fourdiscrete distributions. Hereinafter, the four distributions will berespectively referred to as, in ascending order of threshold voltage, an“S0” state, an “S1” state, an “S2” state, and an “S3” state.

The “S0” state corresponds to, for example, a data erase state. The “S1”to “S3” states correspond to states in which a charge is injected into acharge storage layer and data is written. In the write operation, it isassumed that verify voltages corresponding to the respective thresholdvoltage distributions are V1 to V3. In this case, the voltage valuesestablish a relationship of V1<V2<V3<Vread.

Setting values for the verify voltages and setting values for readvoltages corresponding to the respective states may be either identicalto or different from each other. To simplify the description, a casewill be described in which the setting values for the verify voltagesand the setting values for the read voltages are the same.

Hereinafter, read operations corresponding to the read operations of the“S1” to “S3” states will be respectively referred to as read operationsR1, R2, and R3. In read operation R1, it is determined whether or notthe threshold voltage of the memory cell transistor MC is less than thevoltage V1. In read operation R2, it is determined whether or not thethreshold voltage of the memory cell transistor MC is less than thevoltage V2. In read operation R3, it is determined whether or not thethreshold voltage of the memory cell transistor MC is less than thevoltage V3.

As described above, each memory cell transistor MC belongs to one of thefour threshold voltage distributions, thereby taking one of the fourstates. By allocating these states to “00” to “11” in binary notation,each memory cell transistor MC is capable of storing two bits of data.The two bits of data will be respectively referred to as a lower bit andan upper bit. Furthermore, a group of lower bits that are collectivelywritten into (or read from) the memory group MG is referred to as alower page, and a group of upper bits that are collectively written into(or read from) the memory group MG is referred to as an upper page.

In the example of FIG. 29, data is allocated to the upper bit and thelower bit of each of the memory cell transistors MC that belongs to eachof the threshold voltage distributions in the following manner. Data isallocated to each state to become a Gray code in which one bit of datachanges between two adjacent states.

“S0” state: “11” data

“S1” state: “01” data

“S2” state: “00” data

“S3” state: “10” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operation R2. The upper page isdetermined by read operations R1 and R3. That is, the values of thelower bit and the upper bit are determined by one read operation and tworead operations, respectively. Therefore, the data allocation of thepresent example is a 1-2 coding.

The data allocation to the “S0” to “S3” states is not limited to the 1-2coding.

4.2 Conversion Operation of Logical Page Address and Physical PageAddress

An example of a conversion operation of the logical page address and thephysical page address will be explained with reference to FIGS. 30 and31. FIG. 30 is a diagram explaining a flow of the conversion operationof the logical page address and the physical page address. FIG. 31 is adiagram showing a logical page data allocation with respect to aphysical page.

As shown in FIG. 30, for example, when the memory controller 200receives a write request from the host device 2, it allocates onelogical page address “90001” corresponding to one received logicaladdress “00001”. Hereinafter, an allocated logical page will be referredto as a “logical first page”. In the example of FIG. 30, the logicalfirst page corresponds to the logical page address “90001”.

When the command user interface circuit 121 receives a write orderincluding one page of the logical page address and the logical page fromthe memory controller 200, the command user interface circuit 121converts the one page of the logical page address into two pages of thephysical page address. In the present embodiment, the command userinterface circuit 121 converts the logical page address of the logicalfirst page into physical page addresses of the lower page and the upperpage.

Here, a data length of one page of the logical page and a data length oftwo pages of the physical page are the same. In the present embodiment,since the number of logical pages to be written is a=“1”, and the numberof physical pages to be written is b=“2”, one page of the physical page,that is, a page size n of one memory group MG, can be described byn=m/2. For example, in the case where the page size of the logical pageis 16 [kB], the page size of the physical page is n=16/2=8 [kB].

For example, based on the physical page addresses converted at thecommand user interface circuit 121, the sequencer 123 writes the data ofthe logical first page in the lower page and the upper page of onememory group MG.

The arrangement of the logical page data in one memory group MG will bedescribed in detail.

As shown in FIG. 31, in the present embodiment, data of the logicalfirst page is divided into two pieces of data to become a first clusterand a second cluster from the head data. For example, the memory 100writes the first half of data of the first cluster of the logical firstpage in a first cell area of the lower page, and writes the second halfof data of the first cluster of the logical first page in a second cellarea of the lower page. Furthermore, the memory 100 writes the firsthalf of data of the second cluster of the logical first page in thefirst cell area of the upper page, and writes the second half of data ofthe second cluster of the logical first page in the second cell area ofthe upper page.

4.3 Read Operation

The read operation will be explained. In the present embodiment, thephysical pages to be read with respect to the logical first page are thelower page (the first cell area and the second cell area) and the upperpage (the first cell area and the second cell area). In this case, thememory 100 transmits (outputs) data in the lower page (the first cellarea and the second cell area) and data in the upper page (the firstcell area and the second cell area) to the memory controller 200.

4.3.1 Flow of Read Operation

The flow of the read operation in the memory 100 will first be describedwith reference to FIG. 32. FIG. 32 is a flowchart of the read operation.

As shown in FIG. 32, the memory 100 receives a read order from thememory controller 200 (step S1) The command user interface circuit 121converts the logical page address into the physical page addresses,then, transmits the received command and the converted physical pageaddresses to the sequencer 123.

The sequencer 123 first executes the read operation of the lower page(step S30). More specifically, the sequencer 123 executes the readoperation R2 corresponding to the read voltage V2.

The sequencer 123 determines data of the lower page (data of the firstcluster of the logical first page) based on the result of read operationR2 (step S31).

The sequencer 123 transfers the data of the lower page read by the sensecircuits SA1 and SA2 to the latch circuits ADL1 and the ADL2,respectively (step S32).

The sequencer 123 transfers the data in the latch circuits ADL1 and ADL2(data of the first cluster of the logical first page) to the latchcircuits XDL1 and XDL2, respectively (step S33). The sequencer 123 mayalso transfer the data of the lower page read by the sense circuits SA1and SA2 directly to the latch circuits XDL1 and XDL2, respectively.

The sequencer 123 sets a head address of the latch circuit XDL1 as acolumn address CA in the column counter 125 (step S34). Based on thecolumn address CA incremented by the column counter 125, the serialaccess controller 126 receives data sequentially from the head addressof the latch circuit XDL1 and transfers it to the input/output circuit110. The input/output circuit 110 starts transmitting (outputting) thedata in the latch circuits XDL1 and XDL2 to the memory controller 200.

The sequencer 123 executes the read operation of the upper page inparallel with the data output of the latch circuits XDL1 and XDL2 (stepS35). More specifically, the sequencer 123 executes read operation R1corresponding to read voltage V1, and read operation R3 corresponding toread voltage V3. The order of read operations R1 and R3 maybe setfreely.

The sequencer 123 determines data of the upper page (data of the secondcluster of the logical first page) based on the result of readoperations R1 and R3 (step S36).

The sequencer 123 transfers the data of the upper page read by the sensecircuits SA1 and SA2 to the latch circuits ADL1 and ADL2, respectively(step S37).

In the case where the data output of the latch circuits XDL1 is notended (step S38_No), the sequencer 123 repeats a confirmation operationof the data output until the output is ended.

When the data output of the latch circuits XDL1 is ended (step S38_Yes),the sequencer 123 transfers the data in the latch circuits ADL1 to thelatch circuits XDL1 (step S39). It should be noted that, in the case ofstep S38_Yes, the data output of the latch circuits XDL2 maybe startedsubsequently, and the sequencer 123 may execute step S39 during the dataoutput of the latch circuits XDL2.

In the case where the data output of the latch circuits XDL2 is notended (step S40_No), the sequencer 123 repeats a confirmation operationof the data output until the output is ended.

When the data output of the latch circuits XDL2 is ended (step S40_Yes),the sequencer 123 transfers the data in the latch circuits ADL2 to thelatch circuits XDL2 (step S41). The sequencer 123 ends the readoperation of the logical first page when the data outputs of the latchcircuits XDL1 and XDL2 (data of the second cluster of the logical firstpage) are ended. It should be noted that, in the case of step S40_Yes,the data output of the latch circuits XDL1 may be started subsequently,and the sequencer 123 may execute step S41 during the data output of thelatch circuits XDL1.

4.3.2 Command Sequence of Read Operation

An example of a command sequence of the read operation will be describedwith reference to FIG. 33. FIG. 33 is a command sequence of the readoperation of the logical first page. In the example of FIG. 33, signalsCEn, CLE, ALE, WEn, and REn are omitted to simplify the description. Inaddition, the example of FIG. 33 also shows voltages of the selectedword line WL in a case where an internal RBn signal is in the busystate.

As shown in FIG. 33, first, the memory controller 200 transmits command“00h”. The memory controller 200 then transmits a logical page address“AD-P1” of the logical first page. In the memory 100, the command userinterface circuit 121 converts the received logical page address “AD-P1”into the physical page addresses. The memory controller 200 thentransmits a command “30h” to the memory 100. The command user interfacecircuit 121 sequentially transmits the received command and theconverted physical page addresses to the sequencer 123.

The sequencer 123 starts the read operation in response to the command“30h”. The sequencer 123 first sets the internal RBn signal and theexternal RBn signal to the “L” level indicating the busy state. Thesequencer 123 then executes the read operation of the lower page (readoperation R2). That is, read voltage V2 is applied to the selected wordline WL. The read result of the lower page is stored in the latchcircuits ADL1 and ADL2. The data in the latch circuits ADL1 is thentransferred to the latch circuits XDL1. The data in the latch circuitsADL2 is then transferred to the latch circuits XDL2. When the readoperation of the lower page is ended, the sequencer 123 sets theexternal RBn signal to the “H” level. Furthermore, when the readoperation of the lower page is ended, the sequencer 123 starts the readoperation of the upper page (read operations R1 and R3). That is, readvoltages V1 and V3 are sequentially applied to the selected word lineWL.

When the “H” level external RBn signal is received, the memorycontroller 200 transmits signal REn (not shown) to the memory 100. Theinput/output circuit 110 starts outputting data in accordance withsignal REn. The input/output circuit 110 first outputs the data in thelatch circuits XDL1. When the read operation of the upper page is endedwhile the data in the latch circuits XDL1 is being output, the sequencer123 sets the internal RBn signal to the “H” level. The read result ofthe upper page is stored in the latch circuits ADL1 and ADL2. In thecase where the data output of the latch circuits XDL1 and XDL2 is endedbefore ending the read operation of the upper page, the sequencer 123may temporarily set the external RBn signal to the “L” level (busystate), and suspend the output of data to the memory controller 200.This allows the data of the upper page to be output successively afterthe data of the lower page is output.

When the data output of the latch circuits XDL1 is ended, theinput/output circuit 110 subsequently starts data output of the latchcircuits XDL2. While the data in the latch circuits XDL2 is beingoutput, the data in the latch circuits ADL1 is transferred to the latchcircuits XDL1. When the data output of the latch circuits XDL2 is ended,the input/output circuit 110 subsequently executes output of data in thelatch circuits XDL1. While the data in the latch circuits XDL1 is beingoutput, the data in the latch circuits ADL2 is transferred to the latchcircuits XDL2. When the data output of the latch circuits XDL2 is ended,the read operation of the logical first page is ended. It should benoted that the memory 100 may also set the level of the external RBnsignal to be identical to that of the internal RBn signal, and, afterreading all of the pieces of data, set the external RBn signal (internalRBn signal) to the “H” level and output the data.

4.4 Write Operation

The write operation will be described below. In the present embodiment,the full sequence write operation is executed, in which the data of thelogical first page is collectively written in the memory group MGincluding the lower page and the upper page. That is, two bits of datais collectively written in one memory cell transistor MC. In the fullsequence write operation of the present embodiment, the “S1” to “S3”states are written.

4.4.1 Flow of Write Operation

The flow of the write operation in the memory 100 will be described withreference to FIGS. 34 and 35. FIGS. 34 and 35 are flowcharts of thewrite operation.

As shown in FIGS. 34 and 35, the memory 100 receives a write order ofthe logical first page from the memory controller 200 (step S230). Atthis time, the command user interface circuit 121 converts the logicalpage address of the logical first page into the physical page addresses.

The sequencer 123 sets a head address of the latch circuit XDLI as acolumn address CA in the column counter 125 (step S231).

In the page buffer 133, data input of the first half of a first clusterof the logical first page to the latch circuits XDL1 is started based onthe column address CA received from the column counter 125 (step S232).

In the case where the data input of the first half of the first clusterof the logical first page to the latch circuits XDL1 is not ended (stepS233_No), the sequencer 123 repeats a confirmation operation of the datainput until the input is ended.

When the data input of the first half of the first cluster of thelogical first page to the latch circuits XDL1 is ended (step S233_Yes),the sequencer 123 transfers the data in the latch circuits XDL1 to thelatch circuits ADL1 (step S234). Furthermore, when the data input of thefirst half of the first cluster of the logical first page to the latchcircuits XDL1 is ended, data input of a second half of the first clusterof the logical first page to the latch circuits XDL2 is startedsubsequently. It should be noted that, in the case of step S233_Yes, thesequencer 123 may execute step S234 while the data input of the secondhalf of the first cluster of the logical first page to the latchcircuits XDL2 is subsequently started, and the data input of the latchcircuits XDL2 is being executed.

In the case where the data input of the second half of the first clusterof the logical first page to the latch circuits XDL2 is not ended (stepS235_No), the sequencer 123 repeats a confirmation operation of the datainput until the input is ended.

When the data input of the second half of the first cluster of thelogical first page to the latch circuits XDL2 is ended (step S235_Yes),the sequencer 123 sets a head address of the latch circuit XDL1 as thecolumn address CA in the column counter 125 (step S236). In the pagebuffer 133, data input of a first half of a second cluster of thelogical first page to the latch circuits XDL1 is started based on thecolumn address CA received from the column counter 125.

The sequencer 123 transfers the data of the second half of the firstcluster of the logical first page in the latch circuits XDL2 to thelatch circuits ADL2 while the data input of the first half of the secondcluster of the logical first page to the latch circuits XDL1 is beingexecuted (step S237).

After the data input of the first half of the second cluster of thelogical first page to the latch circuits XDL1 is ended, data input of asecond half of the second cluster of the logical first page to the latchcircuits XDL2 is started. In the case where the data input of the secondhalf of the second cluster of the logical first page to the latchcircuits XDL2 is not ended (step S238_No), the sequencer 123 repeats aconfirmation operation of the data input until the input is ended.

After the data input of the second half of the second cluster of thelogical first page to the latch circuits XDL2 is ended (step S238_Yes),the data input of the logical first page to the latch circuits XDL1 andXDL2 is ended. The sequencer 123 sets the external RBn signal and theinternal RBn signal to the “L” level. The sequencer 123 determines thestate of each of the memory cell transistors MC based on the combinationof data in the lower page and the upper page.

The sequencer 123 executes a program operation based on the determinedstate (step S239).

After ending the program operation, the sequencer 123 executes a programverify operation (step S240).

In the case where the verification is not passed (step S241_No), thesequencer 123 confirms whether or not the number of program loops hasreached the preset upper limit number (step S242).

In the case where the number of program loops has not reached the upperlimit number (step S242_No), the sequencer 123 executes the programoperation (step S239). That is, the sequencer 123 repeats the programloop.

In the case where the number of program loops has reached the upperlimit number (step S242_Yes), the sequencer 123 ends the write operationand reports to the memory controller 200 that the write operation didnot end successfully.

In the case of passing the verification (step S241_Yes), that is, endingwriting of the “S1” to “S3” states, the sequencer 123 sets the externalRBn signal to the “H” level and ends the full sequence write operation.

4.4.2 Command Sequence of Write Operation

An example of a command sequence of the write operation will bedescribed with reference to FIG. 36. FIG. 36 is a command sequence ofthe full sequence write operation. In the example of FIG. 36, signalsCEn, CLE, ALE, WEn, and REn are omitted to simplify the description.

As shown in FIG. 36, the memory controller 200 first transmits a command“80h” to the memory 100. The memory controller 200 then transmits alogical page address “AD-P1” of the logical first page. In the memory100, the command user interface circuit 121 converts the receivedlogical page address “AD-P1” into the physical page addresses. Thememory controller 200 then transmits data of the logical first page tothe memory 100. When data input of the first half of the first clusterof the logical first page to the latch circuits XDL1 is ended, datainput of the second half of the first cluster of the logical first pageto the latch circuits XDL2 is started subsequently. The data stored inthe latch circuits XDL1 is transferred to the latch circuits ADL1 whilethe data of the second half of the first cluster of the logical firstpage is being input to the latch circuits XDL2. When the data input ofthe second half of the first cluster of the logical first page to thelatch circuits XDL2 is ended, data input of the first half of the secondcluster of the logical first page to the latch circuits XDL1 is startedsubsequently. The data stored in the latch circuits XDL2 is transferredto the latch circuits ADL2 while the data of the first half of thesecond cluster of the logical first page is being input to the latchcircuits XDL1. When the data input of the first half of the secondcluster of the logical first page to the latch circuits XDL1 is ended,data input of the second half of the second cluster of the logical firstpage to the latch circuits XDL2 is started subsequently. The secondcluster of the logical first page is stored in the latch circuits XDL1and XDL2.

The memory controller 200 then transmits a command “10h” to the memory100 to instruct execution of the write operation.

When the command “10h” is received, the sequencer 123 sets the internalRBn signal and the external RBn signal to the “L” level. The sequencer123 then determines the state of each of the memory cell transistors MCbased on the data stored in the latch circuits ADL1, ADL2, XDL1, andXDL2, and then executes the write operation. After ending the writeoperation, the sequencer 123 sets the internal RBn signal and theexternal RBn signal to the “H” level.

4.5 Advantageous Effects of Fourth Embodiment

The configuration of the present embodiment can attain the same effectas the first embodiment.

5. Fifth Embodiment

A fifth embodiment will be described. In the fifth embodiment, a case ofallocating data of three logical pages to four physical pages (that is,one memory group MG capable of storing four-page data) will bedescribed. Hereinafter, the description will focus mainly on mattersdifferent from those of the first to fourth embodiments.

5.1 Configurations of Sense Amplifier and Page Buffer

An example of configurations of the sense amplifier 132 and the pagebuffer 133 will be described with reference to FIG. 37. FIG. 37 is ablock diagram of the sense amplifier 132 and the page buffer 133.

As shown in FIG. 37, in the present embodiment, the sequencer 123controls a plurality of memory cell transistors MC in one memory groupMG by dividing them into three areas of a first cell area, a second cellarea, and a third cell area. Similarly, the sequencer 123 controls thesense amplifier 132 and the page buffer 133 by dividing them in three inaccordance with the first to third cell areas. For example, the memorycell transistors MC included in the first cell area are associated withbit lines BL0 to BL (i−1). The memory cell transistors MC included inthe second cell area are associated with bit lines BL (i) to BL(j−1) (jis larger than i and smaller than k). The memory cell transistors MCincluded in the third cell area are associated with bit lines BL (j) toBL (k−1). It should be noted that the number of memory cell transistorsMC included in the first cell area, the number of memory celltransistors MC included in the second cell area, and the number ofmemory cell transistors MC included in the third cell area arepreferably the same. For example, in the case where the number of memorycell transistors MC included in the first cell area, the number ofmemory cell transistors MC included in the second cell area, and thenumber of memory cell transistors MC included in the third cell area arethe same, a relationship such as i=j/2 =k/3 will be established for “i”,“j”, and “k”.

The page buffer 133 of the present embodiment includes latch circuitsADL, BDL, CDL, and XDL for each sense circuit SA. The sense circuit SAand the latch circuits ADL, BDL, CDL, and XDL are coupled to each other.In other words, the sense circuit SA and the latch circuits ADL, BDL,CDL, and XDL are coupled to each other in a manner allowing data to betransmitted and received therebetween. The latch circuits ADL, BDL, CDL,and XDL temporarily store data DAT. For example, the read data confirmedby the sense circuit SA in the read operation is transferred to one ofthe latch circuits ADL, BDL, CDL, and XDL from the sense circuit SA.Hereinafter, a sense circuit coupled to a bit line BL corresponding tothe memory cell transistor MC included in the third cell area will bereferred to as “sense circuit SA3”. The latch circuit CDL correspondingto a sense circuit SA1 will be referred to as a “latch circuit CDL1”.The latch circuit CDL corresponding to a sense circuit SA2 will bereferred to as a “latch circuit CDL2”. The latch circuits ADL, BDL, CDL,and XDL corresponding to a sense circuit SA3 will be referred to as a“latch circuit ADL3”, a “latch circuit BDL3”, a “latch circuit CDL3”,and a “latch circuit XDL3”. Furthermore, in the present embodiment, aset of the sense circuit SA1 and latch circuits ADL1, BDL1, CDL1, andXDL1 will be referred to as a “sense amplifier unit SAU1”. A set of thesense circuit SA2 and latch circuits ADL2, BDL2, CDL2, and XDL2 will bereferred to as a “sense amplifier unit SAU2” A set of the sense circuitSA3 and latch circuits ADL3, BDL3, CDL3, and XDL3 will be referred to asa “sense amplifier unit SAU3”.

In the present embodiment, in the same manner as the plurality of senseamplifier units SAU1 and the plurality of sense amplifier units SAU2,the plurality of sense amplifier units SAU3 are arranged together in onearea.

5.2 Threshold Voltage Distributions of Memory Cell Transistors

Possible threshold voltage distributions of the memory cell transistorsMC will be described with reference to FIG. 38. FIG. 38 is a diagramshowing a relationship between threshold voltage distributions and dataallocations of memory cell transistors MC. Hereinafter, in the presentembodiment, a case will be described in which each memory celltransistor MC is a quad-level cell (QLC) (or referred to as “4bit/Cell”) capable of storing 16 values (four bits) of data.

As shown in FIG. 38, the threshold voltage of each memory celltransistor MC takes a value that falls within, for example, 16 discretedistributions. Hereinafter, the 16 distributions will be referred to asan “S0” state, an “S1” state, an “S2” state, an “S3” state, an “S4”state, an “S5” state, an “S6” state, an “S7” state, an “S8” state, an“S9” state, an “S10” state, an “S11” state, an “S12” state, an “S13”state, an “S14” state, and an and“S15” state, from lower to higherthreshold voltages.

The “S0” state corresponds to, for example, a data erase state. The “S1”to “S15” states correspond to states in which a charge is injected intoa charge storage layer and data is written. In a write operation, it isassumed that verify voltages corresponding to the respective thresholdvoltage distributions are V1 to V15. In this case, the values of thesevoltages satisfy the relation ofV1<V2<V3<V4<V5<V6<V7<V8<V9<V10<V11<V12<V13<V14<V15<Vread. In a readoperation, the voltages V1 to V15 are voltages to be applied to theselected word line WL coupled to a memory cell transistor MC that is tobe read.

More specifically, a threshold voltage that falls within the “S0” stateis less than the voltage V1. A threshold voltage that falls within the“S1” state is equal to or higher than the voltage V1, and less than thevoltage V2. A threshold voltage that falls within the “S2” state isequal to or higher than the voltage V2, and less than the voltage V3. Athreshold voltage that falls within the “S3” state is equal to or higherthan the voltage V3, and less than the voltage V4. A threshold voltagethat falls within the “S4” state is equal to or higher than the voltageV4, and less than the voltage V5. A threshold voltage that falls withinthe “S5” state is equal to or higher than the voltage V5, and less thanthe voltage V6. A threshold voltage that falls within the “S6” state isequal to or higher than the voltage V6, and less than the voltage V7. Athreshold voltage that falls within the “S7” state is equal to or higherthan the voltage V7, and less than the voltage V8. A threshold voltagethat falls within the “S8” state is equal to or higher than the voltageV8, and less than the voltage V9. A threshold voltage that falls withinthe “S9” state is equal to or higher than the voltage V9, and less thanthe voltage V10. A threshold voltage that falls within the “S10” stateis equal to or higher than the voltage V10, and less than the voltageV11. A threshold voltage that falls within the “S11” state is equal toor higher than the voltage V11, and less than the voltage V12. Athreshold voltage that falls within the “S12” state is equal to orhigher than the voltage V12, and less than the voltage V13. A thresholdvoltage that falls within the “S13” state is equal to or higher than thevoltage V13, and less than the voltage V14. A threshold voltage thatfalls within the “S14” state is equal to or higher than the voltage V14,and less than the voltage V15. A threshold voltage that falls within the“S15” state is equal to or higher than the voltage V15, and less thanthe voltage Vread.

It should be noted that setting values for the verify voltages andsetting values for read voltages corresponding to the respective statesmay be either identical to or different from each other. To simplify thedescription, a case will be described in which the setting values forthe verify voltages and the setting values for the read voltages are thesame.

Hereinafter, read operations corresponding to the read operations of the“S1” to “S15” states will be respectively referred to as read operationsR1 to R15. In read operation R1, it is determined whether or not thethreshold voltage of the memory cell transistor MC is less than thevoltage V1. In read operation R2, it is determined whether or not thethreshold voltage of the memory cell transistor MC is less than thevoltage V2. The same applies to the subsequent read operations. In eachof the read operations R3 to R15, it is determined whether or not thethreshold voltage of the memory cell transistor MC is less than voltagesV3 to V15, respectively.

As described above, each memory cell transistor MC belongs to one of the16 threshold voltage distributions, thereby taking one of the 16 states.By allocating these states from “0000” to “1111” in binary notation,each memory cell transistor MC is capable of storing four bits of data.Hereinafter, the four bits of data will be respectively referred to as a“lower bit”, a “middle bit”, an “upper bit”, and a “top bit”. A group oflower bits that are collectively written into (or read from) a memorygroup MG is referred to as a “lower page”, a group of middle bits thatare collectively written into (or read from) a memory group MG will bereferred to as a “middle page”, a group of upper bits that arecollectively written into (or read from) a memory group MG will bereferred to as an “upper page”, and a group of top bits that arecollectively written into (or read from) a memory group MG will bereferred to as a “top page”.

In the example of FIG. 38, data is allocated to the “top bit/upperbit/middle bit/lower bit” of each of the memory cell transistors MC thatbelongs to each of the threshold voltage distributions in the followingmanner. Data is allocated to each state to become a Gray code in whichone bit of data changes between two adjacent states.

“S0” state: “1111” data

“S1” state: “0111” data

“S2” state: “0011” data

“S3” state: “0001” data

“S4” state: “0101” data

“S5” state: “1101” data

“S6” state: “1001” data

“S7” state: “1011” data

“S8” state: “1010” data

“S9” state: “1110” data

“S10” state: “0110” data

“S11” state: “0100” data

“S12” state: “1100” data

“S13” state: “1000” data

“S14” state: “0000” data

“S15” state: “0010” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operation R8. The middle page isdetermined by read operations R3, R7, R11, and R15. The upper page isdetermined by read operations R2, R4, R6, R9, and R13. The top page isdetermined by read operations R1, R5, R10, R12, and R14. That is, thevalues of the lower bit, the middle bit, the upper bit, and the top bitare determined by one read operation, four read operations, five readoperations, and five read operations, respectively. That is, the numberof boundaries (hereinafter referred to as a “boundary number”) is one,four, five, and five for the lower bit, the middle bit, the upper bit,and the top bit, respectively. Therefore, the data allocation of thepresent example is a 1-4-5-5 coding.

In the present embodiment, when allocating data for the top bit, theupper bit, the middle bit, and the lower bit, one bit whose boundarynumber is one is included. Furthermore, the boundary number of a bitwhose boundary number is not one is coded in a manner such that themaximum value of the boundary number becomes minimum. For example, inthe case of a QLC, that is, 4 bit/Cell, since the overall boundarynumber is 15, when sharing the remaining boundary number 14, with theremaining three bits, the maximum value of the boundary number willbecome minimum if the boundary number of each bit is set to four, five,and five.

The data allocation to the “S0” to “S15” states is not limited to the1-4-5-5 coding.

5.3 Conversion Operation of Logical Page Address and Physical PageAddress

An example of a conversion operation of the logical page address and thephysical page address will be explained with reference to FIG. 39 andFIG. 40. FIG. 39 is a diagram explaining a flow of the conversionoperation of the logical page address and the physical page address.FIG. 40 is a diagram showing the logical page data allocation withrespect to the physical page.

As shown in FIG. 39, for example, when the memory controller 200receives a write request from the host device 2, the memory controller200 allocates three logical page addresses “90001”, “90002”, and “90003”corresponding to three received logical addresses “00001”, “00002”, and“00003”. Hereinafter, the three allocated logical pages will be referredto as a “logical first page”, a “logical second page”, and a “logicalthird page”. In the example of FIG. 39, the logical first pagecorresponds to the logical page address “90001”, the logical second pagecorresponds to the logical page address “90002”, and the logical thirdpage corresponds to the logical page address “90003”.

When the command user interface circuit 121 receives a write orderincluding three pages of the logical page address and the logical pagefrom the memory controller 200, the command user interface circuit 121converts the three pages of the logical page address into four pages ofthe physical page address. In the present embodiment, the command userinterface circuit 121 converts the logical page address of the logicalfirst page into a first cell area of the lower page and a physical pageaddress of the middle page. The command user interface circuit 121converts the logical page address of the logical second page into thephysical page addresses of the second cell area of the lower page andthe upper page. Furthermore, the command user interface circuit 121converts the logical page address of the logical third page into thephysical page addresses of the third cell area of the lower page and thetop page.

At this time, a data length of three pages of the logical page and adata length of four pages of the physical page are the same. In thepresent embodiment, since the number of logical pages to be written isa=“3”, and the number of physical pages to be written is b=“4”, one pageof the physical page, that is, a page size n of one memory group MG, canbe described by n=m×¾. Furthermore, each of the page size of the firstto the third cell areas may be described by n/3 For example, in the casewhere the page size of the logical page is 16 [kB], the page size of thephysical page is n=16×¾=12 [kB].

For example, based on the physical page address converted at the commanduser interface circuit 121, the sequencer 123 writes the data of thelogical first page in the first cell area of the lower page and thefirst to the third cell areas of the middle page of one memory group MG.The sequencer 123 writes data of the logical second page in the secondcell area of the lower page and the first to the third cell areas of theupper page. The sequencer 123 writes data of the logical third page inthe third cell area of the lower page and the first to the third cellareas of the top page.

The arrangement of the logical page data in one memory group MG will bedescribed in detail.

As shown in FIG. 40, in the present embodiment, data of the logicalfirst page, data of the logical second page, and data of the logicalthird page are divided respectively into four pieces of a first clusterto a fourth cluster from the head. For example, the memory 100 writesthe first cluster of the logical first page in the first cell area ofthe lower page, writes the second cluster of the logical first page inthe second cell area of the middle page, writes the third cluster of thelogical first page in the third cell area of the middle page, and writesthe fourth cluster of the logical first page in the first cell area ofthe middle page. The memory 100 writes the first cluster of the logicalsecond page in the second cell area of the lower page, writes the secondcluster of the logical second page in the third cell area of the upperpage, writes the third cluster of the logical second page in the firstcell area of the upper page, and writes the fourth cluster of thelogical second page in the second cell area of the upper page. Thememory 100 writes the first cluster of the logical third page in thethird cell area of the lower page, writes the second cluster of thelogical third page in the first cell area of the top page, writes thethird cluster of the logical third page in the second cell area of thetop page, and writes the fourth cluster of the logical third page in thethird cell area of the top page.

5.4 Read Operation

The read operation will be explained. In the present embodiment, theread operations differ depending on whether the logical page to be readis a logical first page, a logical second page, or a logical third page.In the case where the logical page is the logical first page, thephysical pages to be read are the lower page (the first cell area) andthe middle page (the first cell area to the third cell area) In thiscase, the memory 100 transmits (outputs) data in the first cell area ofthe lower page and data in the first cell area to the third cell area ofthe middle page to the memory controller 200. In the case where thelogical page is the logical second page, the physical pages to be readare the lower page (the second cell area) and the upper page (the firstcell area to the third cell area). In this case, the memory 100transmits (outputs) data in the second cell area of the lower page anddata in the first cell area to the third cell area of the upper page tothe memory controller 200. Furthermore, in the case where the logicalpage is the logical third page, the physical pages to be read are thelower page (the third cell area) and the top page (the first cell areato the third cell area). In this case, the memory 100 transmits(outputs) data in the third cell area of the lower page and data in thefirst cell area to the third cell area of the top page to the memorycontroller 200.

5.4.1 Flow of Read Operation

The flow of the read operation in the memory 100 will first be describedwith reference to FIGS. 41 to 43. FIGS. 41 to 43 are flowcharts of theread operation.

As shown in FIGS. 41 to 43, the memory 100 receives a read order of thelogical first page, the logical second page, or the logical third pagefrom the memory controller 200 (step Si). The command user interfacecircuit 121 converts the logical page address into the physical pageaddresses, then transmits the received command and the convertedphysical page addresses to the sequencer 123.

In the case where the logical page address is the logical page addressof the logical first page (step S50_Yes), the sequencer 123 firstexecutes the read operation of the lower page (step S51). Morespecifically, the sequencer 123 executes read operation R8 correspondingto read voltage V8.

The sequencer 123 determines the data of the lower page based on theresult of read operation R8 (step S52).

The sequencer 123 transfers the data of the lower page read by the sensecircuits SA1 to SA3 to the latch circuits ADL1 to ADL3, respectively(step S53).

The sequencer 123 transfers the data in the latch circuits ADL1 (data ofthe first cluster of the logical first page) to the latch circuits XDL1(step S54).

The sequencer 123 sets a head address of the latch circuit XDL1 as acolumn address CA in the column counter 125 (step S55). Based on thecolumn address CA incremented by the column counter 125, the serialaccess controller 126 receives data sequentially from the head addressof the latch circuit XDL1 and transfers it to the input/output circuit110. The input/output circuit 110 starts transmitting (outputting) thedata in the latch circuits XDL1 to the memory controller 200. Here,although the data in the latch circuits ADL1 is transferred to the latchcircuits XDL1 after the data of the lower page read by the sensecircuits SA1 to SA3 is transferred to the latch circuits ADL1 to ADL3,the sequencer 123 may also transfer the data in the sense circuits SA1directly to the latch circuits XDL1.

The sequencer 123 executes the read operation of the middle page inparallel with the data output of the latch circuits XDL1 (step S56).More specifically, the sequencer 123 executes read operation R3corresponding to read voltage V3, read operation R7 corresponding toread voltage V7, read operation R11 corresponding to read voltage V11,and read operation R15 corresponding to read voltage V15. The order ofread operations R3, R7, R11, and R15 may be set freely.

The sequencer 123 determines the data of the middle page based on theresults of read operations R3, R7, R11, and R15 (step S57).

The sequencer 123 transfers the data of the middle page read by thesense circuits SA1 to SA3 to the latch circuits ADL1 to ADL3,respectively (step S58).

The sequencer 123 transfers the data in the latch circuits ADL2 and ADL3(data of the second and third clusters of the logical first page) to thelatch circuits XDL2 and XDL3, respectively (step S59).

In the case where the data output of the latch circuits XDL1 (data ofthe first cluster of the logical first page) is not ended (step S60_No),the sequencer 123 repeats a confirmation operation of the data outputuntil the output is ended.

When the data output of the latch circuits XDL1 is ended (step S60_Yes),the sequencer 123 transfers the data in the latch circuits ADL1 (data ofthe fourth cluster of the logical first page) to the latch circuits XDL1(step S61). When the data output of the latch circuits XDL2 and XDL3 isended, the sequencer 123 sets a head address of the latch circuit XDL1as the column address CA in the column counter 125. When the data outputof the latch circuits XDL1 is ended, the sequencer 123 ends the readoperation of the logical first page.

In the case where the logical page address is the logical page addressof the logical second page (step S50_No and step S62_Yes), the sequencer123 executes the read operation of the lower page (step S63) in the samemanner as step S51.

The sequencer 123 determines the data of the lower page based on theresult of read operation R8 (step S64)

The sequencer 123 transfers the data of the lower page read by the sensecircuits SA1 to SA3 to the latch circuits ADL1 to ADL3, respectively(step S65).

The sequencer 123 transfers the data in the latch circuits ADL2 (data ofthe first cluster of the logical second page) to the latch circuits XDL2(step S66). Here, although the data in the latch circuits ADL2 istransferred to the latch circuits XDL2 after the data of the lower pageread by the sense circuits SA1 to SA3 is transferred to the latchcircuits ADL1 to ADL3, the sequencer 123 may also transfer the data inthe sense circuits SA2 directly to the latch circuits XDL2.

The sequencer 123 sets a head address of the latch circuit XDL2 as acolumn address CA in the column counter 125 (step S67). Based on thecolumn address CA incremented by the column counter 125, the serialaccess controller 126 receives data sequentially from the head addressof the latch circuit XDL2 and transfers it to the input/output circuit110. The input/output circuit 110 starts transmitting (outputting) thedata in the latch circuits XDL2 to the memory controller 200.

The sequencer 123 executes the read operation of the upper page inparallel with the data output of the latch circuits XDL2 (step S68).More specifically, the sequencer 123 executes read operation R2corresponding to read voltage V2, read operation R4 corresponding toread voltage V4, read operation R6 corresponding to read voltage V6,read operation R9 corresponding to read voltage V9, and read operationR13 corresponding to read voltage V13. The order of read operations R2,R4, R6, R9, and R13 may be set freely.

The sequencer 123 determines the data of the upper page based on theresult of read operations R2, R4, R6, R9, and R13 (step S69).

The sequencer 123 transfers the data of the upper page read by the sensecircuits SA1 to SA3 to the latch circuits ADL1 to ADL3, respectively(step S70).

The sequencer 123 transfers the data in the latch circuits ADL1 and ADL3(data of the second and third clusters of the logical second page) tothe latch circuits XDL1 and XDL3, respectively (step S71).

In the case where the data output of the latch circuits XDL2 (data ofthe first cluster of the logical second page) is not ended (stepS72_No), the sequencer 123 repeats a confirmation operation of the dataoutput until the output is ended.

When the data output of the latch circuits XDL2 is ended (step S72_Yes),the sequencer 123 transfers the data in the latch circuits ADL2 (data ofthe fourth cluster of the logical second page) to the latch circuitsXDL2 (step S73). When the data output of the latch circuits XDL3 (dataof the second cluster of the logical second page) is ended, thesequencer 123 sets a head address of the latch circuit XDL1 as thecolumn address CA in the column counter 125. The sequencer 123 then endsthe read operation of the logical second page when the data output ofthe latch circuits XDL1 (data of the third cluster of the logical secondpage) and the data output of the latch circuits XDL2 (data of the fourthcluster of the logical second page) are ended.

In the case where the logical page address is the logical page addressof the logical third page (step S50_No and step S62_No), the sequencer123 executes the read operation of the lower page (step S74) in the samemanner as step S51.

The sequencer 123 determines the data of the lower page based on theresult of read operation R8 (step S74).

The sequencer 123 transfers the data of the lower page read by the sensecircuits SA1 to SA3 to the latch circuits ADL1 to ADL3, respectively(step S76).

The sequencer 123 transfers the data in the latch circuits ADL3 (data ofthe first cluster of the logical third page) to the latch circuits XDL3(step S77). Here, although the data in the latch circuits ADL3 istransferred to the latch circuits XDL3 after the data of the lower pageread by the sense circuits SA1 to SA3 is transferred to the latchcircuits ADL1 to ADL3, the sequencer 123 may also transfer the data inthe sense circuits SA3 directly to the latch circuits XDL3.

The sequencer 123 sets a head address of the latch circuit XDL3 as acolumn address CA in the column counter 125 (step S78). Based on thecolumn address CA incremented by the column counter 125, the serialaccess controller 126 receives data sequentially from the head addressof the latch circuit XDL3 and transfers it to the input/output circuit110. The input/output circuit 110 starts transmitting (outputting) thedata in the latch circuits XDL3 to the memory controller 200.

The sequencer 123 executes the read operation of the top page inparallel with the data output of the latch circuits XDL3 (step S79).More specifically, the sequencer 123 executes read operation R1corresponding to read voltage V1, read operation R5 corresponding toread voltage V5, read operation R10 corresponding to read voltage V10,read operation R12 corresponding to read voltage V12, and read operationR14 corresponding to read voltage V14. The order of read operations R1,R5, R10, R12, and R14 may be set freely.

The sequencer 123 determines the data of the top page based on theresult of read operations R1, R5, R10, R12, and R14 (step S80).

The sequencer 123 transfers the data of the top page read by the sensecircuits SA1 to SA3 to the latch circuits ADL1 to ADL3, respectively(step S81).

The sequencer 123 transfers the data in the latch circuits ADL1 and ADL2(data of the second and third clusters of the logical third page) to thelatch circuits XDL1 and XDL2, respectively (step S82).

In the case where the data output of the latch circuits XDL3 (data ofthe first cluster of the logical third page) is not ended (step S83_No),the sequencer 123 repeats a confirmation operation of the data outputuntil the output is ended.

When the data output of the latch circuits XDL3 is ended (step S83_Yes),the sequencer 123 transfers the data in the latch circuits ADL3 (data ofthe fourth cluster of the logical second page) to the latch circuitsXDL3 (step S84). Furthermore, when the data output of the latch circuitsXDL3 (data of the first cluster of the logical third page) is ended, thesequencer 123 sets a head address of the latch circuit XDL1 as thecolumn address CA in the column counter 125. The sequencer 123 then endsthe read operation of the logical third page when the data output of thelatch circuits XDL1 (data of the second cluster of the logical thirdpage), the data output of the latch circuits XDL2 (data of the thirdcluster of the logical third page), and the data output of the latchcircuits XDL3 (data of the fourth cluster of the logical third page) areended.

5.4.2 Command Sequence of Read Operation

An example of a command sequence of the read operation will be describedwith reference to in FIGS. 44 to 46. FIG. 44 is a command sequence ofthe read operation of the logical first page. FIG. 45 is a commandsequence of the read operation of the logical second page. FIG. 46 is acommand sequence of the read operation of the logical third page. In theexamples of FIGS. 44 to 46, signals CEn, CLE, ALE, WEn, and REn areomitted to simplify the description. In the examples of FIGS. 44 to 46,some of the commands and addresses are omitted. In addition, theexamples of FIGS. 44 to 46 also show voltages of the selected word lineWL in a case where an internal RBn signal is in the busy state.

The command sequence in the read operation of the logical first pagewill first be explained.

As shown in FIG. 44, the sequencer 123 starts the read operation inresponse to a command “30h”. The sequencer 123 first sets the internalRBn signal and the external RBn signal to the “L” level indicating thebusy state. The sequencer 123 then executes the read operation of thelower page (read operation R8). That is, read voltage V8 is applied tothe selected word line WL. The read result of the lower page is storedin the latch circuits ADL1 to ADL3. The data in the latch circuits ADL1is then transferred to the latch circuits XDL1. When the read operationof the lower page is ended, the sequencer 123 sets the external RBnsignal to the “H” level indicating the ready state. Furthermore, whenthe read operation of the lower page is ended, the sequencer 123 startsthe read operation of the middle page (read operations R3, R7, R11, andR15). That is, read voltages V3, V7, V11, and V15 are sequentiallyapplied to the selected word line WL.

When the “H” level external RBn signal is received, the memorycontroller 200 transmits signal REn (not shown) to the memory 100. Theinput/output circuit 110 starts outputting data in accordance withsignal REn. The input/output circuit 110 first outputs the data in thelatch circuits XDL1. When the data output of the latch circuits XDL1 isended while the read operation of the middle page is executed, thesequencer 123 temporarily sets the external RBn signal to the “L” leveluntil the read operation of the middle page is ended.

The read result of the middle page is stored in the latch circuits ADL1to ADL3. The data in the latch circuits ADL1 to ADL3 is then transferredto the latch circuits XDL1 to XDL3. When the read operation of themiddle page is ended, the sequencer 123 sets the external RBn signal andthe internal RBn signal to the “H” level.

When the “H” level external RBn signal is received, the memorycontroller 200 resumes transmission of signal REn (not shown). Theinput/output circuit 110 outputs data in the order of the latch circuitsXDL2, XDL3, and XDL1 in accordance with signal REn. When the data outputof the latch circuits XDL1 is ended, the read operation of the logicalfirst page is ended. It should be noted that the memory 100 may also setthe level of the external RBn signal to be identical to that of theinternal RBn signal, and, after reading all of the pieces of data, setthe external RBn signal (internal RBn signal) to the “H” level andoutput the data.

A command sequence in the read operation of the logical second page willbe explained.

As shown in FIG. 45, the sequencer 123 starts the read operation inresponse to a command “30h”. The sequencer 123 first sets the internalRBn signal and the external RBn signal to the “L” level indicating thebusy state. The sequencer 123 then executes the read operation of thelower page (read operation R8). That is, the read voltage V8 is appliedto the selected word line WL. The read result of the lower page isstored in the latch circuits ADL1 to ADL3. The data in the latchcircuits ADL2 is then transferred to the latch circuits XDL2. When theread operation of the lower page is ended, the sequencer 123 sets theexternal RBn signal to the “H” level indicating the ready state.Furthermore, when the read operation of the lower page is ended, thesequencer 123 starts the read operation of the upper page (readoperations R2, R4, R6, R9, and R13). That is, read voltages V2, V4, V6,V9, and V13 are sequentially applied to the selected word line WL.

When the “H” level external RBn signal is received, the memorycontroller 200 transmits signal REn (not shown) to the memory 100. Theinput/output circuit 110 starts outputting data in accordance withsignal REn. The input/output circuit 110 first outputs the data in thelatch circuits XDL2. When the data output of the latch circuits XDL2 isended while the read operation of the upper page is executed, thesequencer 123 temporarily sets the external RBn signal to the “L” leveluntil the read operation of the upper page is ended.

The read result of the upper page is stored in the latch circuits ADL1to ADL3. The data in the latch circuits ADL1 to ADL3 is then transferredto the latch circuits XDL1 to XDL3 When the read operation of the upperpage is ended, the sequencer 123 sets the external RBn signal and theinternal RBn signal to the “H” level.

When the “H” level external RBn signal is received, the memorycontroller 200 resumes transmission of signal REn (not shown). Theinput/output circuit 110 outputs data in the order of the latch circuitsXDL3, XDL1, and XDL2 in accordance with signal REn. When data output ofthe latch circuits XDL2 is ended, the read operation of the logicalsecond page is ended. It should be noted that the memory 100 may alsoset the level of the external RBn signal to be identical to that of theinternal RBn signal, and, after reading all of the pieces of data, setthe external RBn signal (internal RBn signal) to the “H” level andoutput the data.

A command sequence in the read operation of the logical third page willbe explained.

As shown in FIG. 46, the sequencer 123 starts the read operation inresponse to a command “30h”. The sequencer 123 first sets the internalRBn signal and the external RBn signal to the “L” level, indicating thebusy state. The sequencer 123 then executes the read operation of thelower page (read operation R8). That is, the read voltage V8 is appliedto the selected word line WL. The read result of the lower page isstored in the latch circuits ADL1 to ADL3. The data in the latchcircuits ADL3 is then transferred to the latch circuits XDL3. When theread operation of the lower page is ended, the sequencer 123 sets theexternal RBn signal to the “H” level indicating the ready state.Furthermore, when the read operation of the lower page is ended, thesequencer 123 starts the read operation of the top page (read operationsR1, R5, R10, R12, and R14). That is, read voltages V1, V5, V10, V12, andV14 are sequentially applied to the selected word line WL.

When the “H” level external RBn signal is received, the memorycontroller 200 transmits signal REn (not shown) to the memory 100. Theinput/output circuit 110 starts outputting data in accordance withsignal REn. The input/output circuit 110 first outputs the data in thelatch circuits XDL3. When the data output of the latch circuits XDL3 isended while the read operation of the top page is executed, thesequencer 123 temporarily sets the external RBn signal to the “L” leveluntil the read operation of the top page is ended.

The read result of the top page is stored in the latch circuits ADL1 toADL3. The data in the latch circuits ADL1 to ADL3 is then transferred tothe latch circuits XDL1 to XDL3. When the read operation of the top pageis ended, the sequencer 123 sets the external RBn signal and theinternal RBn signal to the “H” level.

When the “H” level external RBn signal is received, the memorycontroller 200 resumes transmission of signal REn (not shown). Theinput/output circuit 110 outputs data in the order of the latch circuitsXDL1, XDL2, and XDL 3 in accordance with signal REn. When the dataoutput of the latch circuits XDL3 is ended, the read operation of thelogical third page is ended. It should be noted that the memory 100 mayalso set the level of the external RBn signal to be identical to that ofthe internal RBn signal, and, after reading all of the pieces of data,set the external RBn signal (internal RBn signal) to the “H” level andoutput the data.

5.5 Write Operation

The write operation will be described below. In the present embodiment,the full sequence write operation is executed, in which the data of thelogical first page to the logical third page is collectively written inthe memory group MG including the lower page, the middle page, the upperpage, and the top page. That is, four bits of data is collectivelywritten in one memory cell transistor MC. In the full sequence writeoperation of the present embodiment, the “S1” to “S15” states arewritten.

5.5.1 Flow of Write Operation

The flow of the write operation in the memory 100 will be described withreference to FIGS. 47 to 49. FIGS. 47 to 49 are flowcharts of the writeoperation.

As shown in FIGS. 47 to 49, when receiving the write order, the memory100 receives the logical page address of the logical first page from thememory controller 200 (step S251). The command user interface circuit121 converts the logical page address of the logical first page into thephysical page addresses.

The sequencer 123 sets a head address of the latch circuit XDL1 as acolumn address CA in the column counter 125 (step S252)

In the page buffer 133, data input of the first cluster of the logicalfirst page to the latch circuits XDL1 is started based on the columnaddress CA received from the column counter 125 (step S253)

In the case where the data input of the first cluster of the logicalfirst page to the latch circuits XDL1 is not ended (step S254_No), thesequencer 123 repeats a confirmation operation of the data input untilthe input is ended.

When the data input to the latch circuits XDL1 is ended (step S254_Yes),the sequencer 123 transfers the data in the latch circuits XDL1 to thelatch circuits ADL1 (step S255). Furthermore, when the data input to thelatch circuits XDL1 is ended, data input of the second cluster of thelogical first page to the latch circuits XDL2 and data input of thethird cluster of the logical first page to the latch circuits XDL3 areexecuted in sequence.

In the case where the data input of the third cluster of the logicalfirst page to the latch circuits XDL3 is not ended (step S256_No), thesequencer 123 repeats a confirmation operation of the data input untilthe input is ended.

When the data input to the latch circuits XDL3 is ended (step S256_Yes),the sequencer 123 sets a head address of the latch circuit XDL1 as thecolumn address CA in the column counter 125 (step S257).

In the page buffer 133, data input of the fourth cluster of the logicalfirst page to the latch circuits XDL1 is started based on the columnaddress CA received from the column counter 125.

In the case where the data input of the fourth cluster of the logicalfirst page to the latch circuits XDL1 is not ended (step S258_No), thesequencer 123 repeats a confirmation operation of the data input untilthe input is ended.

When the data input to the latch circuits XDL1 is ended (step S258_Yes),the data input of the logical first page to the latch circuits XDL1 toXDL3 is ended.

The sequencer 123 transfers the data in the latch circuits XDL1 to XDL3to the latch circuits BDL1 to BDL3, respectively (step S259). The datainput of the logical first page is thus ended. It should be noted thatthe sequencer 123 may also transfer the data from the latch circuitsXDL1 to the latch circuits ADL1 during the data input to the latchcircuits XDL2, transfer the data from the latch circuits XDL2 to thelatch circuits BDL2 during the data input to the latch circuits XDL3,transfer the data from the latch circuits XDL3 to the latch circuitsBDL3 during the data input to the latch circuits XDL1, and transfer thedata from the latch circuits XDL1 to the latch circuits BDL1 during thedata input to the latch circuit XDL2.

The memory 100 then receives the logical page address of the logicalsecond page from the memory controller 200 (step S260). At this time,the command user interface circuit 121 converts the logical page addressof the logical second page into the physical page addresses.

The sequencer 123 sets a head address of the latch circuit XDL2 as acolumn address CA in the column counter 125 (step S261).

In the page buffer 133, data input of the first cluster of the logicalsecond page to the latch circuits XDL2 is started based on the columnaddress CA received from the column counter 125 (step S262).

In the case where the data input of the first cluster of the logicalsecond page to the latch circuits XDL2 is not ended (step S263_No), thesequencer 123 repeats a confirmation operation of the data input untilthe input is ended.

When the data input of the first cluster of the logical second page tothe latch circuits XDL2 is ended (step S263_Yes), the sequencer 123transfers the data in the latch circuits XDL2 to the latch circuits ADL2(step S264). Furthermore, when the data input to the latch circuits XDL2is ended, data input of the second cluster of the logical second page tothe latch circuits XDL3 is executed subsequently.

In the case where the data input of the second cluster of the logicalsecond page to the latch circuits XDL3 is not ended (step S265_No), thesequencer 123 repeats a confirmation operation of the data input untilthe input is ended.

When the data input of the second cluster of the logical second page tothe latch circuits XDL3 is ended (step S265_Yes), the sequencer 123 setsa head address of the latch circuit XDL1 as the column address CA in thecolumn counter 125 (step S266). In the page buffer 133, data input ofthe third cluster of the logical second page to the latch circuits XDL1and data input of the fourth cluster of the logical second page to thelatch circuits XDL2 are sequentially executed based on the columnaddress CA received from the column counter 125.

In the case where the data input of the fourth cluster of the logicalsecond page to the latch circuits XDL2 is not ended (step S267_No), thesequencer 123 repeats a confirmation operation of the data input untilthe input is ended.

When the data input of the fourth cluster of the logical second page tothe latch circuits XDL2 is ended (step S267_Yes), the data input of thelogical second page to the latch circuits XDL1 to XDL3 is ended.

The sequencer 123 transfers the data in the latch circuits XDL1 to XDL3to the latch circuits CDL1 to CDL3, respectively (step S268). It shouldbe noted that the sequencer 123 may also transfer the data from thelatch circuits XDL2 to the latch circuits ADL2 during the data input tothe latch circuits XDL3, transfer the data from the latch circuits XDL3to the latch circuits BDL3 during the data input to the latch circuitsXDL1, transfer the data from the latch circuits XDL1 to the latchcircuits BDL1 during the data input to the latch circuits XDL2, andtransfer the data from the latch circuits XDL2 to the latch circuit BDL2during the data input to the latch circuit XDL3.

The memory 100 then receives the logical page address of the logicalthird page from the memory controller 200 (step S269) At this time, thecommand user interface circuit 121 converts the logical page address ofthe logical third page into the physical page addresses.

The sequencer 123 sets a head address of the latch circuit XDL3 as acolumn address CA in the column counter 125 (step S270)

In the page buffer 133, data input of the first cluster of the logicalthird page to the latch circuits XDL3 is started based on the columnaddress CA received from the column counter 125 (step S271).

In the case where the data input of the first cluster of the logicalthird page to the latch circuits XDL3 is not ended (step S272_No), thesequencer 123 repeats a confirmation operation of the data input untilthe input is ended.

When the data input of the first cluster of the logical third page tothe latch circuits XDL3 is ended (step S272_Yes), the sequencer 123transfers the data in the latch circuits XDL3 to the latch circuits ADL3(step S273).

The sequencer 123 sets a head address of the latch circuit

XDL1 as a column address CA in the column counter 125 (step S274). Inthe page buffer 133, data input of the second cluster of the logicalthird page to the latch circuits XDL1, data input of the third clusterof the logical third page to the latch circuits XDL2, and data input ofthe fourth cluster of the logical third page to the latch circuits XDL3are sequentially executed based on the column address CA received fromthe column counter 125.

In the case where the data input of the fourth cluster of the logicalthird page to the latch circuits XDL3 is not ended (step S275_No), thesequencer 123 repeats a confirmation operation of the data input untilthe input is ended.

When the data input of the fourth cluster of the logical third page tothe latch circuits XDL3 is ended (step S275_Yes) the data input of thelogical third page to the latch circuits XDL1 to XDL3 is ended. Thesequencer 123 sets the external RBn signal to the “L” level. Thesequencer 123 then determines the state of each of the memory celltransistors MC based on the input data of the logical first page to thelogical third page, that is, the combination of data in the lower page,the middle page, the upper page, and the top page. It should be notedthat the sequencer 123 may also transfer data from the latch circuitsXDL3 to the latch circuits ADL3 during the data input to the latchcircuits XDL1.

The sequencer 123 executes the program operation based on the determinedstate (step S276).

After ending the program operation, the sequencer 123 executes a programverify operation (step S277).

In the case where the verification is not passed (step S278_No), thesequencer 123 confirms whether or not the number of program loops hasreached a preset upper limit number (step S279).

In the case where the number of program loops has not reached the upperlimit number (step S279_No), the sequencer 123 executes the programoperation (step S276). That is, the sequencer 123 repeats the programloop.

In the case where the number of program loops has reached the upperlimit number (step S279_Yes), the sequencer 123 ends the write operationand reports to the memory controller 200 that the write operation didnot end successfully.

In the case of passing the verification (step S278_Yes), that is, endingwriting of the “S1” to “S15” states, the sequencer 123 sets the externalRBn signal to the “H” level and ends the full sequence write operation.

5.5.2 Command Sequence of Write Operation

An example of a command sequence of the write operation will bedescribed with reference to FIG. 50. FIG. 50 is a command sequence ofthe full sequence write operation. In the example of FIG. 50, signalsCEn, CLE, ALE, WEn, and REn are omitted to simplify the description.

As shown in FIG. 50, the memory controller 200 first transmits a command“80h” to the memory 100. The memory controller 200 then transmits alogical page address “AD-P1” of the logical first page. In the memory100, the command user interface circuit 121 converts the receivedlogical page address “AD-P1” into the physical page addresses.

The memory controller 200 then transmits data of the logical first pageto the memory 100. The first cluster of the logical first page is storedin the latch circuits XDL1, and is then transferred to the latchcircuits ADL1. The second cluster and the third cluster of the logicalfirst page are stored in the latch circuits XDL2 and XDL3, and are thentransferred to the latch circuits BDL2 and BDL3. The fourth cluster ofthe logical first page is stored in the latch circuits XDL1, and is thentransferred to the latch circuits BDL1.

The memory controller 200 then transmits a command “1Ah” to the memory100 to notify data input of the next logical page. The memory controller200 then transmits the command “80h” and a logical page address “AD-P2”of the logical second page to the memory 100. In the memory 100, thecommand user interface circuit 121 converts the received logical pageaddress “AD-P2” into the physical page addresses.

The memory controller 200 then transmits data of the logical second pageto the memory 100. The first cluster of the logical second page isstored in the latch circuits XDL2, and is then transferred to the latchcircuits ADL2. The second cluster of the logical second page is storedin the latch circuits XDL3, and is then transferred to the latchcircuits CRL3. The third cluster of the logical second page is stored inthe latch circuits XDL1, and is then transferred to the latch circuitsCDL1. The fourth cluster of the logical second page is stored in thelatch circuits XDL2, and is then transferred to the latch circuits CDL2.

The memory controller 200 then transmits the command “1Ah” to the memory100 to notify data input of the next logical page. The memory controller200 then transmits the command “80h” and a logical page address “AD-P3”of the logical third page to the memory 100. In the memory 100, thecommand user interface circuit 121 converts the received logical pageaddress “AD-P3” into the physical page addresses.

The memory controller 200 then transmits data of the logical third pageto the memory 100. The first cluster of the logical third page is storedin the latch circuits XDL3, and is then transferred to the latchcircuits ADL3. The second cluster of the logical third page is stored inthe latch circuits XDL1. The third cluster of the logical third page isstored in the latch circuits XDL2. The fourth cluster of the logicalthird page is stored in the latch circuits XDL3.

The memory controller 200 then transmits a command “10h” to the memory100 to instruct execution of the write operation.

When the command “10h” is received, the sequencer 123 sets the internalRBn signal and the external RBn signal to the “L” level. The sequencer123 then determines the state of each of the memory cell transistors MCbased on the data stored in the latch circuits ADL1 to ADL3, BDL1 toBDL3, CDL1 to CDL3, and XDL1 to XDL3, and then executes the writeoperation. After ending the write operation, the sequencer 123 sets theinternal RBn signal and the external RBn signal to the “H” level.

5.6 Advantageous Effects of Fifth Embodiment

The configuration of the present embodiment can attain the same effectas the first embodiment.

6. Sixth Embodiment

A sixth embodiment will be described. In the sixth embodiment, twelveexamples will be given for a QLC coding that is different from the fifthembodiment. In each example, when allocating data for the top bit, theupper bit, the middle bit, and the lower bit, one bit whose boundarynumber is one is included. Furthermore, the boundary number of a bitwhose boundary number is not one is coded in a manner such that themaximum value of the boundary number becomes minimum. Hereinafter, thedescription will focus mainly on matters different from those of thefifth embodiment.

6.1 First Example

A first example of the coding will first be described with reference toFIG. 51. FIG. 51 is a table showing data allocations to each state.

As shown in FIG. 51, in the present embodiment, in the same manner asthe fifth embodiment, data is allocated to each state to become a Graycode in which one bit of data changes between two adjacent states.

“S0” state: “1111” data

“S1” state: “0111” data

“S2” state: “0011” data

“S3” state: “0001” data

“S4” state: “0101” data

“S5” state: “1101” data

“S6” state: “1001” data

“S7” state: “1011” data

“S8” state: “1010” data

“S9” state: “1000” data

“S10” state: “0000” data

“S11” state: “0010” data

“S12” state: “0110” data

“S13” state: “1110” data

“S14” state: “1100” data

“S15” state: “0100” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operation R8. The middle page isdetermined by read operations R3, R7, R9, R11, and R14. The upper pageis determined by read operations R2, R4, R6, and R12. A top page isdetermined by read operations R1, R5, R10, R13, and R15. Therefore, thedata allocation of the present example is a 1-5-4-5 coding.

6.2 Second Example

A second example of the coding will be described with reference to FIG.52. FIG. 52 is a table showing data allocations to each state.

As shown in FIG. 52, in the present embodiment, in the same manner asthe fifth embodiment, data is allocated to each state to become a Graycode in which one bit of data changes between two adjacent states.

“S0” state: “1111” data

“S1” state: “0111” data

“S2” state: “0011” data

“S3” state: “0001” data

“S4” state: “0101” data

“S5” state: “1101” data

“S6” state: “1001” data

“S7” state: “1011” data

“S8” state: “1010” data

“S9” state: “1110” data

“S10” state: “1100” data

“S11” state: “0100” data

“S12” state: “0110” data

“S13” state: “0010” data

“S14” state: “0000” data

“S15” state: “1000” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operation R8. The middle page isdetermined by read operations R3, R7, R10, R12, and R14. The upper pageis determined by read operations R2, R4, R6, R9, and R13. The top pageis determined by read operations R1, R5, R11, and R15. Therefore, thedata allocation of the present example is a 1-5-5-4 coding.

6.3 Third Example

A third example of the coding will be described with reference to FIG.53. FIG. 53 is a table showing data allocations to each state.

As shown in FIG. 53, in the present embodiment, in the same manner asthe fifth embodiment, data is allocated to each state to become a Graycode in which one bit of data changes between two adjacent states.

“S0” state: “1111” data

“S1” state: “0111” data

“S2” state: “0011” data

“S3” state: “0001” data

“S4” state: “0101” data

“S5” state: “1101” data

“S6” state: “1001” data

“S7” state: “1011” data

“S8” state: “1010” data

“S9” state: “0010” data

“S10” state: “0000” data

“S11” state: “0100” data

“S12” state: “0110” data

“S13” state: “1110” data

“S14” state: “1100” data

“S15” state: “1000” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operation R8. The middle page isdetermined by read operations R3, R7, R10, R12, and R14. The upper pageis determined by read operations R2, R4, R6, R11, and R15. The top pageis determined by read operations R1, R5, R9, and R13. Therefore, thedata allocation of the present example is a 1-5-5-4 coding.

6.4 Fourth Example

A fourth example of the coding will be described with reference to FIG.54. FIG. 54 is a table showing data allocations to each state.

As shown in FIG. 54, in the present embodiment, in the same manner asthe fifth embodiment, data is allocated to each state to become a Graycode in which one bit of data changes between two adjacent states.

“S0” state: “1111” data

“S1” state: “0111” data

“S2” state: “0011” data

“S3” state: “1011” data

“S4” state: “1001” data

“S5” state: “1101” data

“S6” state: “0101” data

“S7” state: “0001” data

“S8” state: “0000” data

“S9” state: “0010” data

“S10” state: “0110” data

“S11” state: “0100” data

“S12” state: “1100” data

“S13” state: “1110” data

“S14” state: “1010” data

“S15” state: “1000” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operation R8. The middle page isdetermined by read operations R4, R9, R11, R13, and R15. The upper pageis determined by read operations R2, R5, R7, R10, and R14. The top pageis determined by read operations R1, R3, R6, and R12. Therefore, thedata allocation of the present example is a 1-5-5-4 coding.

6.5 Fifth Example

A fifth example of the coding will be described with reference to FIG.55. FIG. 55 is a table showing data allocations to each state.

As shown in FIG. 55, in the present embodiment, in the same manner asthe fifth embodiment, data is allocated to each state to become a Graycode in which one bit of data changes between two adjacent states.

“S0” state: “1111” data

“S1” state: “0111” data

“S2” state: “0011” data

“S3” state: “1011” data

“S4” state: “1001” data

“S5” state: “1101” data

“86” state: “0101” data

“S7” state: “0001” data

“S8” state: “0000” data

“S9” state: “0010” data

“S10” state: “1010” data

“S11” state: “1000” data

“S12” state: “1100” data

“S13” state: “1110” data

“S14” state: “0110” data

“S15” state: “0100” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operation R8. The middle page isdetermined by read operations R4, R9, R11, R13, and R15. The upper pageis determined by read operations R2, R5, R7, and R12. The top page isdetermined by read operations R1, R3, R6, R10, and R14. Therefore, thedata allocation of the present example is a 1-5-4-5 coding.

6.6 Sixth Example

A sixth example of the coding will be described with reference to FIG.56. FIG. 56 is a table showing data allocations to each state.

As shown in FIG. 56, in the present embodiment, in the same manner asthe fifth embodiment, data is allocated to each state to become a Graycode in which one bit of data changes between two adjacent states.

“S0” state: “1111” data

“S1” state: “0111” data

“S2” state: “0011” data

“S3” state: “1011” data

“S4” state: “1001” data

“S5” state: “0001” data

“S6” state: “0101” data

“S7” state: “1101” data

“S8” state: “1100” data

“S9” state: “1110” data

“S10” state: “1010” data

“S11” state: “1000” data

“S12” state: “0000” data

“S13” state: “0010” data

“S14” state: “0110” data

“S15” state: “0100” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operation R8. The middle page isdetermined by read operations R4, R9, R11, R13, and R15. The upper pageis determined by read operations R2, R6, R10, and R14. The top page isdetermined by read operations R1, R3, R5, R7, and R12. Therefore, thedata allocation of the present example is a 1-5-4-5 coding.

6.7 Seventh Example

A seventh example of the coding will be described with reference to FIG.57. FIG. 57 is a table showing data allocations to each state.

As shown in FIG. 57, in the present embodiment, in the same manner asthe fifth embodiment, data is allocated to each state to become a Graycode in which one bit of data changes between two adjacent states.

“S0” state: “1111” data

“S1” state: “0111” data

“S2” state: “0011” data

“S3” state: “1011” data

“S4” state: “1001” data

“S5” state: “0001” data

“S6” state: “0101” data

“S7” state: “1101” data

“S8” state: “1100” data

“S9” state: “1000” data

“S10” state: “1010” data

“S11” state: “1110” data

“S12” state: “0110” data

“S13” state: “0100” data

“S14” state: “0000” data

“S15” state: “0010” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operation R8. The middle page isdetermined by read operations R4, R10, R13, and R15. The upper page isdetermined by read operations R2, R6, R9, R11, and R14. The top page isdetermined by read operations R1, R3, R5, R7, and R12. Therefore, thedata allocation of the present example is a 1-4-5-5 coding.

6.8 Eighth Example

An eighth example of the coding will be described with reference to FIG.58. FIG. 58 is a table showing data allocations to each state.

As shown in FIG. 58, in the present embodiment, in the same manner asthe fifth embodiment, data is allocated to each state to become a Graycode in which one bit of data changes between two adjacent states.

“S0” state: “1111” data

“S1” state: “0111” data

“S2” state: “0011” data

“S3” state: “0001” data

“S4” state: “0101” data

“S5” state: “1101” data

“S6” state: “1001” data

“S7” state: “1011” data

“S8” state: “1010” data

“S9” state: “1000” data

“S10” state: “0000” data

“S11” state: “0100” data

“S12” state: “1100” data

“S13” state: “1110” data

“S14” state: “0110” data

“S15” state: “0010” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operation R8. The middle page isdetermined by read operations R3, R7, R9, and R13. The upper page isdetermined by read operations R2, R4, R6, R11, and R14. The top page isdetermined by read operations R1, R5, R10, R12, and R14. Therefore, thedata allocation of the present example is a 1-4-5-5 coding.

6.9 Ninth Example

A ninth example of the coding will be described with reference to FIG.59. FIG. 59 is a table showing data allocations to each state.

As shown in FIG. 59, in the present embodiment, in the same manner asthe fifth embodiment, data is allocated to each state to become a Graycode in which one bit of data changes between two adjacent states.

“S0” state: “1111” data

“S1” state: “0111” data

“S2” state: “0011” data

“S3” state: “1011” data

“S4” state: “1001” data

“S5” state: “0001” data

“S6” state: “0101” data

“S7” state: “1101” data

“S8” state: “1100” data

“S9” state: “1110” data

“S10” state: “1010” data

“S11” state: “1000” data

“S12” state: “0000” data

“S13” state: “0100” data

“S14” state: “0110” data

“S15” state: “0010” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operation R8. The middle page isdetermined by read operations R4, R9, R11, and R14. The upper page isdetermined by read operations R2, R6, R10, R13, and R15. The top page isdetermined by read operations R1, R3, R5, R7, and R12. Therefore, thedata allocation of the present example is a 1-4-5-5 coding.

6.10 Tenth Example

A tenth example of the coding will be described with reference to FIG.60. FIG. 60 is a table showing data allocations to each state.

As shown in FIG. 60, in the present embodiment, in the same manner asthe fifth embodiment, data is allocated to each state to become a Graycode in which one bit of data changes between two adjacent states.

“S0” state: “1111” data

“S1” state: “0111” data

“S2” state: “0011” data

“S3” state: “0001” data

“S4” state: “0101” data

“S5” state: “1101” data

“S6” state: “1001” data

“S7” state: “1011” data

“S8” state: “1010” data

“S9” state: “0010” data

“S10” state: “0000” data

“S11” state: “1000” data

“S12” state: “1100” data

“S13” state: “1110” data

“S14” state: “0110” data

“S15” state: “0100” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operation R8. The middle page isdetermined by read operations R3, R7, R10, R13, and R15. The upper pageis determined by read operations R2, R4, R6, and R12. The top page isdetermined by read operations R1, R5, R9, R11, and R14. Therefore, thedata allocation of the present example is a 1-5-4-5 coding.

6.11 Eleventh Example

An eleventh example of the coding will be described with reference toFIG. 61. FIG. 61 is a table showing data allocations to each state.

As shown in FIG. 61, in the present embodiment, in the same manner asthe fifth embodiment, data is allocated to each state to become a Graycode in which one bit of data changes between two adjacent states.

“S0” state: “1111” data

“S1” state: “0111” data

“S2” state: “0011” data

“S3” state: “1011” data

“S4” state: “1001” data

“S5” state: “1101” data

“S6” state: “0101” data

“S7” state: “0001” data

“S8” state: “0000” data

“S9” state: “0100” data

“S10” state: “0110” data

“S11” state: “1110” data

“S12” state: “1100” data

“S13” state: “1000” data

“S14” state: “1010” data

“S15” state: “0010” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operation R8. The middle page isdetermined by read operations R4, R10, R12, and R14. The upper page isdetermined by read operations R2, R5, R7, R9, and R13. The top page isdetermined by read operations R1, R3, R6, R11, and R15. Therefore, thedata allocation of the present example is a 1-4-5-5 coding.

6.12 Twelfth Example

A twelfth example of the coding will be described with reference to FIG.62. FIG. 62 is a table showing data allocations to each state.

As shown in FIG. 62, in the present embodiment, in the same manner asthe fifth embodiment, data is allocated to each state to become a Graycode in which one bit of data changes between two adjacent states.

“S0” state: “1111” data

“S1” state: “0111” data

“S2” state: “0011” data

“S3” state: “1011” data

“S4” state: “1001” data

“S5” state: “1101” data

“S6” state: “0101” data

“S7” state: “0001” data

“S8” state: “0000” data

“S9” state: “1000” data

“S10” state: “1010” data

“S11” state: “1110” data

“S12” state: “1100” data

“S13” state: “0100” data

“S14” state: “0110” data

“S15” state: “0010” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operation R8. The middle page isdetermined by read operations R4, R10, R12, and R14. The upper page isdetermined by read operations R2, R5, R7, R11, and R15. The top page isdetermined by read operations R1, R3, R6, R9, and R13. Therefore, thedata allocation of the present example is a 1-4-5-5 coding.

6.13 Advantageous Effects of Sixth Embodiment

The coding of the present embodiment is applicable to the fifthembodiment.

The configuration of the present embodiment can attain the same effectas the first embodiment.

7. Seventh Embodiment

A seventh embodiment will be described. In the seventh embodiment, twoexamples will be given to explain the QLC read operation that isdifferent from that of the fifth embodiment. Hereinafter, thedescription will focus mainly on matters different from those of thefifth embodiment.

7.1 First Example

The read operation of a first example will first be explained. In thefirst example, a case in which the order of the read voltages to beapplied to the selected word line WL is different from that of the fifthembodiment in read operations of the logical first page to the logicalthird page will be explained with reference to FIGS. 63 to 65. FIG. 63is a command sequence of the read operation of the logical first page.FIG. 64 is a command sequence of the read operation of the logicalsecond page. FIG. 65 is a command sequence of the read operation of thelogical third page. In the examples of FIGS. 63 to 65, signals CEn, CLE,ALE, WEn, and REn are omitted to simplify the description. In theexamples of FIGS. 63 to 65, some of the commands and addresses areomitted. In addition, the examples of FIGS. 63 to 65 also show voltagesof the selected word line WL in a case where an internal RBn signal isin the busy state.

The command sequence in the read operation of the logical first pagewill first be explained.

As shown in FIG. 63, in the read operation of the lower page (readoperation R8) and the read operation of the middle page (read operationsR3, R7, R11, and R15) corresponding to the logical first page, thesequencer 123 executes the read operations in the order of R15, R11, R8,R7, and R3. That is, read voltages V15, V11, V8, V7, and V3 aresequentially applied to the selected word line WL. After ending readoperation R3, the sequencer 123 sets an external RBn signal and theinternal RBn signal to the “H” level. Therefore, after the readoperation of the middle page is ended, output of the read data isstarted.

It should be noted that the sequencer 123 may also execute the readoperation in the order of R3, R7, R8, R11, and R15. That is, readvoltages V3, V7, V8, V11, and V15 may be sequentially applied to theselected word line WL. When read operation R8 is executed, data of thelower page is determined. Therefore, the sequencer 123 may set theexternal RBn signal to the “H” level and output the data.

The command sequence in the read operation of the logical second pagewill be explained.

As shown in FIG. 64, in the read operation of the lower page (readoperation R8) and the read operation of the upper page (read operationsR2, R4, R6, R9, and R13) corresponding to the logical second page, thesequencer 123 executes the read operations in the order of R13, R9, R8,R6, R4, and R2. That is, read voltages V13, V9, V8, V6, V4, and V2 aresequentially applied to the selected word line WL. After ending thewrite operation R2, the sequencer 123 sets the external RBn signal andthe internal RBn signal to the “H” level. Therefore, after the readoperation of the upper page is ended, output of the read data isstarted.

It should be noted that the sequencer 123 may also execute the readoperation in the order of R2, R4, R6, R8, R9, and R13. That is, readvoltages V2, V4, V6, V8, V9, and V13 may be sequentially applied to theselected word line WL. When read operation R8 is executed, data of thelower page is determined. Therefore, the sequencer 123 may set theexternal RBn signal to the “H” level and output the data.

The command sequence in the read operation of the logical third pagewill be explained.

As shown in FIG. 65, in the read operation of the lower page (readoperation R8) and the read operation of the top page (read operationsR1, R5, R10, R12, and R14) corresponding to the logical third page, thesequencer 123 executes the read operations in the order of R14, R12,R10, R8, R5, and R1. That is, read voltages V14, V12, V10, V8, V5, andV1 are sequentially applied to the selected word line WL. After endingthe write operation R1, the sequencer 123 sets the external RBn signaland the internal REn signal to the “H” level. Therefore, after the readoperation of the top page is ended, output of the read data is started.

It should be noted that the sequencer 123 may also execute the readoperation in the order of R1, R5, R8, R10, R12, and R14. That is, readvoltages V1, V5, V8, V10, V12, and V14 may be sequentially applied tothe selected word line WL. When read operation R8 is executed, data ofthe lower page is determined. Therefore, the sequencer 123 may set theexternal RBn signal to the “H” level and output the data.

7.2 Second Example

The read operation of a second example will be explained. In the secondexample, a case in which pieces of data of the lower page, the middlepage, the upper page, and the top page are collectively read in thesequential read operation will be explained with reference to FIG. 66.In the sequential read operation of the present example, “S0” to “S15”states are collectively read. FIG. 66 is a command sequence of thesequential read operation. In the example of FIG. 66, signals CEn, CLE,ALE, WEn, and REn are omitted to simplify the description. In theexample of FIG. 66, some of the commands and addresses are omitted. Inaddition, the example of FIG. 66 also shows voltages of the selectedword line WL in a case where an internal RBn signal is in the busystate.

As shown in FIG. 66, when the sequencer 123 receives a command “30h”, itstarts the read operation in response to the command. The sequencer 123first sets the internal RBn signal and the external RBn signal to the“L” level indicating the busy state. The sequencer 123 then executes thesequential read operation. More specifically, the sequencer 123sequentially executes read operations R1 to R15. At this time, readvoltages V1 to V15 are sequentially applied to the selected word lineWL. When read operation R8 is ended, the sequencer 123 determines thedata of the lower page and sets the external RBn signal to the “H”level. The data of the lower page is stored in latch circuits ADL1 toADL3. The data in the latch circuits ADL1 (data of the first cluster ofthe logical first page) is transferred to the latch circuits XDL1 Whenthe “H” level external RBn signal is received, the memory controller 200transmits signal REn (not shown) to the memory 100. The input/outputcircuit 110 starts outputting the data in the latch circuit XDL1 (thedata of the first cluster of the logical first page) in accordance withthe signal REn.

When the data output of the latch circuits XDL1 is ended while thesequential read operation is executed, the sequencer 123 temporarilysets the external RBn signal to the “L” level until the sequential readis ended.

When read operation R13 is ended, the sequencer 123 determines data ofthe upper page. The data of the upper page is stored in latch circuitsCDL1 to CDL3. When read operation R.15 is ended, the sequencer 123determines data of the middle page. The data of the middle page isstored in latch circuits BDL1 to BDL3. The data in the latch circuitsBDL2 (data of the second cluster of the logical first page) istransferred to the latch circuits XDL2. The data in the latch circuitsBDL3 (data of the third cluster of the logical first page) istransferred to the latch circuits XDL3. The data in the latch circuitsBDL1 (data of the fourth cluster of the logical first page) istransferred to the latch circuits XDL1.

When the sequential read operation is ended, the sequencer 123 sets theexternal RBn signal and the internal RBn signal to the “H” level.

When the “H” level external RBn signal is received, the memorycontroller 200 resumes transmission of signal REn (not shown). Theinput/output circuit 110 outputs data in the order of the latch circuitsXDL2, XDL3, and XDL1 in accordance with the signal REn. When data outputof the latch circuits XDL1 (the data of the fourth cluster of thelogical first page) is ended, the data output of the logical first pageis ended.

Subsequently, data output of the logical second page is started. Thedata in the latch circuits ADL2 (data of the first cluster of thelogical second page) is transferred to the latch circuits XDL2. The datain the latch circuits CDL3 (data of the second cluster of the logicalsecond page) is transferred to the latch circuits XDL3. The data in thelatch circuits CDL1 (data of the third cluster of the logical secondpage) is transferred to the latch circuits XDL1. The data is output inthe order of the latch circuits XDL2, XDL3, and XDL1. When the dataoutput of the latch circuits XDL2 (the data of the first cluster of thelogical second page) is ended, data in the latch circuits CDL2 (data ofthe fourth cluster of the logical second page) is transferred to thelatch circuits XDL2. When data output of the latch circuits XDL1 (thedata of the third cluster of the logical second page) is ended, the datain the latch circuits XDL2 (the data of the fourth cluster of thelogical second page) is output. When data output of the latch circuitsXDL2 is ended, the data output of the logical second page is ended.

Subsequently, data output of the logical third page is started. The datain the latch circuits ADL3 (data of the first cluster of the logicalthird page) is transferred to the latch circuits XDL3. Data in the sensecircuits SA1 (data of the second cluster of the logical third page) istransferred to the latch circuit the XDL1. Data in the sense circuitsSA2 (data of the third cluster of the logical third page) is transferredto the latch circuits XDL2. The data is output in the order of the latchcircuits XDL3, XDL1, and XDL2. When the data output of the latchcircuits XDL3 (the data of the first cluster of the logical third page)is ended, data in the sense circuits SA3 is transferred to the latchcircuits XDL3. When the data output of the latch circuits XDL2 (the dataof the third cluster of the logical third page) is ended, the data inthe latch circuits XDL3 (data of the fourth cluster of the logical thirdpage) is output. When the data output of the latch circuits XDL3 isended, the data output of the logical third page is ended. It should benoted that, in the sequential read operation, the states may also beread collectively in the order of the “S15” state to the “S0” state.

7.3 Advantageous Effects of Seventh Embodiment

The configuration of the present embodiment can attain the same effectas the first embodiment.

8. Eighth Embodiment

An eighth embodiment will be described. The eighth embodiment explains acase in which the logical page data allocation in the physical page isdifferent from the first embodiment. Hereinafter, the description willfocus mainly on matters different from those of the first embodiment.

8.1 Conversion Operation of Logical Page Address and Physical PageAddress

An example of the conversion operation of the logical page address andthe physical page address will be explained with reference to FIGS. 67and 68. FIG. 67 is a diagram explaining a flow of the conversionoperation of the logical page address and the physical page address.FIG. 68 is a diagram showing the logical page data allocation withrespect to the physical page.

In the present embodiment, in the same manner as the first embodiment, acase of allocating data of two logical pages to three physical pages(that is, one memory group MG capable of storing three-page data) willbe described.

As shown in FIG. 67, when the command user interface circuit 121receives a write order including two pages of the logical page addressand the logical page from the memory controller 200, it converts the twopages of the logical page address into three pages of the physical pageaddress. In the present embodiment, the command user interface circuit121 converts the logical page address of the logical first page into thephysical page addresses of the first cell area of the lower page, thefirst cell area of the middle page, and the first cell area of the upperpage. In addition, the command user interface circuit 121 converts thelogical page address of the logical second page into the physical pageaddresses of the second cell area of the lower page, the second cellarea of the middle page, and the second cell area of the upper page.

For example, based on the physical page address converted in the commanduser interface circuit 121, the sequencer 123 writes data of the logicalfirst page in the first cell area of the lower page, the first cell areaof the middle page, and the first cell area of the upper page, andwrites data of the logical second page in the second cell area of thelower page, the second cell area of the middle page, and the second cellarea of the upper page of the memory group MG.

The arrangement of the logical page data in one memory group MG will bedescribed in detail.

As shown in FIG. 68, for example, the memory 100 writes the firstcluster of the logical first page in the first cell area of the lowerpage, writes the second cluster of the logical first page in the firstcell area of the middle page, and writes the third cluster of thelogical first page in the first cell area of the upper page.Furthermore, the memory 100 writes the first cluster of the logicalsecond page in the second cell area of the lower page, writes the secondcluster of the logical second page in the second cell area of the middlepage, and writes the third cluster of the logical second page in thesecond cell area of the upper page.

8.2 Advantageous Effects of Eighth Embodiment

The configuration of the present embodiment can attain the same effectas the first embodiment

9. Ninth Embodiment

A ninth embodiment will be described. In the ninth embodiment, threeconfiguration examples of the sense amplifier 132 and the page buffer133 differing from the first embodiment will be described. Hereinafter,the description will focus mainly on matters different from those of thefirst embodiment.

9.1 First Example

A first example of configurations of the sense amplifier 132 and thepage buffer 133 will first be described with reference to FIG. 69. FIG.69 is a block diagram of the sense amplifier 132 and the page buffer133. In the example of FIG. 69, bit lines BL are omitted to simplify thedescription.

As shown in FIG. 69, in the present example, the first cell area and thesense amplifier unit SAU1 corresponding to the first cell area, and thesecond cell area and the sense amplifier unit SAU2 corresponding to thesecond cell area are arranged alternately. Accordingly, in a memorygroup MG, for example, memory cell transistors MC coupled toeven-numbered bit lines BL are included in the first cell area, andmemory cell transistors MC coupled to odd-numbered bit lines BL areincluded in the second cell area. Latch circuits XDL (XDL1 and XDL2) arecoupled to the serial access controller 126 via a data bus, and are usedfor transmitting/receiving data between the serial access controller 126and the sense amplifier 132.

9.2 Second Example

A second example of configurations of the sense amplifier 132 and thepage buffer 133 will be described with reference to FIG. 70. FIG. 70 isa block diagram of the sense amplifier 132 and the page buffer 133. Inthe example of FIG. 70, bit lines BL are omitted to simplify thedescription.

As shown in FIG. 70, in the present example, latch circuits ADL (ADL1and ADL2) and latch circuits XDL (XDL1 and XDL2) are coupled to theserial access controller 126 via the data bus, and are used fortransmitting/receiving data between the serial access controller 126 andthe sense amplifier 132.

It should be noted that latch circuits BDL (BDL1 and BDL2) and latchcircuits XDL (XDL1 and XDL2) may also be coupled to the serial accesscontroller 126 via the data bus.

9.3 Third Example

A third example of configurations of the sense amplifier 132 and thepage buffer 133 will be described with reference to FIG. 71. FIG. 71 isa block diagram of the sense amplifier 132 and the page buffer 133. Inthe example of FIG. 71, bit lines BL are omitted to simplify thedescription.

As shown in FIG. 71, in the present example, latch circuits ADL (ADL1and ADL2), latch circuits BDL (BDL1 and BDL2), and latch circuits XDL(XDL1 and XDL2) are coupled to the serial access controller 126 via thedata bus, and are used for transmitting/receiving data between theserial access controller 126 and the sense amplifier 132.

9.4 Advantageous Effects of Ninth Embodiment

The configuration of the present embodiment can attain the same effectas the first embodiment.

Furthermore, according to the configuration of the first example of thepresent embodiment, the sense amplifier unit SAU1 and the senseamplifier unit SAU2 can be arranged alternately. This allows data to betransferred between the sense amplifier unit SAUI and the senseamplifier unit SAU2. Such a physically divided arrangement is performedfor various reasons such as to improve a response speed of a circuit,facilitate an interconnect layout between circuits, and facilitatecalculations between latch circuits.

Furthermore, according to the configurations of the second example andthe third example of the present embodiment, the latch circuits ADLand/or the latch circuits BDL are coupled to the serial accesscontroller 126 via the data bus. Therefore, the latch circuits ADLand/or the latch circuits BDL can transmit/receive data to/from theserial access controller 126 without using the latch circuits XDL.Therefore, the operation speed can be improved. Furthermore, since afrequency of transferring data can be reduced, power consumption can bereduced. It should be noted that, in the case of the QLC, the pagebuffer 133 may include the latch circuit CDL in addition to the latchcircuits ADL, BDL, and XDL.

The first example and the second example or the third example of thepresent embodiment may also be combined.

10. Tenth Embodiment

A tenth embodiment will be described. In the tenth embodiment, a case ofapplying different codings between the first cell area and the secondcell area will be described. Hereinafter, the description will focusmainly on matters different from those of the first embodiment.

10.1 Conversion Operation of Logical Page Address and Physical PageAddress

An example of a conversion operation of the logical page address and thephysical page address will first be explained with reference to FIG. 72.FIG. 72 is a diagram showing the logical page data allocation withrespect to the physical page.

In the present embodiment, a case of allocating data of two logicalpages to three physical pages (that is, one memory group MG capable ofstoring three-page data) will be described.

As shown in FIG. 72, data of the logical first page and data of thelogical second page are divided respectively into three pieces of thefirst cluster to the third cluster from the head. For example, thememory 100 writes the first cluster of the logical first page in thefirst cell area of the lower page, writes the second cluster of thelogical first page in the second cell area of the lower page, and writesthe third cluster of the logical first page in the first cell area ofthe middle page. The memory 100 also writes the first cluster of thelogical second page in the second cell area of the middle page, writesthe second cluster of the logical second page in the first cell area ofthe upper page, and writes the third cluster of the logical second pagein the second cell area of the upper page.

10.2 Coding of Memory Cell Transistors

Coding of memory cell transistors MC will be described with reference toFIG. 73. FIG. 73 is a table showing data allocations to each state.

As shown in FIG. 73, in the present embodiment, different codings areapplied between the first cell area and the second cell area. In thiscase, each of the codings is selected so that positions of boundariesdetermining data of the logical page become the same between the firstcell area and the second cell area in the read operation of the logicalpage.

More specifically, in the case of the read operation of the logicalfirst page, positions of the boundary for determining data of the lowerpage and the middle page in the first cell area and positions of theboundary for determining data of the lower page in the second cell areaare the same. Furthermore, in the case of the read operation of thelogical second page, positions of the boundary for determining data ofthe upper page in the first cell area and positions of the boundary fordetermining data of the middle page and the upper page in the secondcell area are the same.

For example, in the first cell area, data is allocated to the “upperbit/middle bit/lower bit” of the memory cell transistor MC in thefollowing manner.

“S0” state: “111” data

“S1” state: “011” data

“S2” state: “001” data

“S3” state: “101” data

“S4” state: “100” data

“S5” state: “000” data

“S6” state: “010” data

“S7” state: “110” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operation R4.

The middle page is determined by read operations R2 and R6. The upperpage is determined by read operations R1, R3, R5, and R7. Therefore, thedata allocation of the the first cell area is a 1-2-4 coding.

Furthermore, in the second cell area, data is allocated to the “upperbit/middle bit/lower bit” of the memory cell transistor MC in thefollowing manner.

“S0” state: “111” data

“S1” state: “101” data

“S2” state: “100” data

“S3” state: “000” data

“S4” state: “001” data

“S5” state: “011” data

“S6” state: “010” data

“S7” state: “110” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operations R2, R4, and R6. The middlepage is determined by read operations R1 and R5. The upper page isdetermined by read operations R3 and R7. Therefore, the data allocationof the the second cell area is a 3-2-2 coding.

In the case of performing the read operation of the logical first page,the target of the read operation is the first and second cell areas ofthe lower page and the first cell area of the middle page. In the firstarea, data of the lower page is determined by read operation R4. Data ofthe middle page is determined by read operations R2 and R6. Furthermore,in the second cell area, data of the lower page is determined by readoperations R2, R4, and R6. Therefore, in both the first cell area andthe second cell area, data of the logical first page is determined byread operations R2, R4, and R6. In the read operation of the logicalfirst page, read voltages may be applied to the selected word line WL inthe order of voltages V2, V4, and V6, or in the order of voltages V6,V4, and V2. Furthermore, when read operation R4 is ended, data of thefirst cluster of the logical first page is determined. Therefore, thememory 100 may output this data to the outside by transferring the datato the latch circuits XDL.

In the case of performing the read operation of the logical second page,the target of the read operation is the second cell area of the middlepage and the first and second cell areas of the upper page. In the firstcell area, data of the upper page is determined by read operations R1,R3, R5, and R7. In the second cell area, data of the middle page isdetermined by read operations R1 and R5. Data of the upper page isdetermined by read operations R3 and R7. Therefore, in both the firstcell area and the second cell area, data of the logical second page isdetermined by read operations R1, R3, R5, and R7. It should be notedthat, in the read operation of the logical second page, read voltagesmay be applied to the selected word line WL in the order of voltages V1,V3, VS, and V7, or in the order of voltages V7, V5, V3, and V1. Forexample, in the case of applying the read voltages to the selected wordline WL in the order of voltages V1, V3, V5, and V7, data of the firstcluster of the logical second page is determined when read operations R1and R5 are ended. Therefore, the memory 100 may output this data to theoutside by transferring the data to the latch circuits XDL. For example,in the case of applying the read voltages to the selected word line WLin the order of voltages V7, V5, V3, and V1, data of the third clusterof the logical second page is determined when read operations R7 and R3are ended. Therefore, the memory 100 may output this data to the outsideby transferring the data to the latch circuits XDL. In this case, forexample, in the memory 100, the allocation of the first cluster of thelogical second page and the allocation of the third cluster of thelogical second page explained with reference to FIG. 72 may be switched.By switching the allocations, the memory 100 can output to the outsidedata of the first cluster of the logical second page earlier than beforeswitching the allocations.

10.3 Advantageous Effects of Tenth Embodiment

The configuration of the present embodiment can attain the same effectas the first embodiment.

Furthermore, according to the configuration of the present embodiment,different codings can be applied for each cell area. Furthermore, in theread operation of the logical page, codings can be selected so thatpositions of boundaries determining the data of the logical page becomethe same in each cell area. This allows the number of boundaries to beminimized in the case of reading data of a plurality of physical pagesin the read operation of the logical page. Therefore, processing abilitycan be improved since the increase in the number of read operations canbe suppressed. For example, in the case of the present embodiment, dataof the logical first page can be determined by performing the readoperation three times, and data of the logical second page can bedetermined by performing the read operation four times.

11. Eleventh Embodiment

An eleventh embodiment will be described. In the eleventh embodiment, acase of allocating data of one logical page to a plurality of physicalpages will be described by three examples. Hereinafter, the descriptionwill focus mainly on matters different from those of the first to tenthembodiments.

11.1 First Example

A first example of a conversion operation of the logical page addressand the physical page address will first be explained with reference toFIG. 74. FIG. 74 is a diagram showing the logical page data allocationwith respect to the physical page.

In the present example, a case of allocating data of one logical page tothree physical pages (that is, one memory group MG capable of storingthree-page data) will be described.

As shown in FIG. 74, data of the logical first page is dividedrespectively into three pieces of the first cluster to the third clusterfrom the head. For example, the memory 100 writes the first cluster ofthe logical first page to the lower page, writes the second cluster ofthe logical first page to the middle page, and writes the third clusterof the logical first page to the upper page.

11.2 Second Example

A second example of the conversion operation of the logical page addressand the physical page address will be explained.

In the present example, a case of allocating data of one logical page tofour physical pages (that is, one memory group MG capable of storingfour-page data) will be described.

An example of possible threshold voltage distributions of memory celltransistors MC of the present example will first be described withreference to FIG. 75. FIG. 75 is a diagram showing a relationshipbetween threshold voltage distributions and data allocations of thememory cell transistors MC.

As shown in FIG. 75, in the present example, data is allocated to the“top bit/upper bit/middle bit/lower bit” of each of the memory celltransistors MC that belongs to each of the threshold voltagedistributions in the following manner. Data is allocated to each stateto become a Gray code in which one bit of data changes between twoadjacent states.

“S0” state: “1111” data

“S1” state: “0111” data

“S2” state: “0101” data

“S3” state: “1101” data

“S4” state: “1100” data

“S5” state: “1000” data

“S6” state: “1001” data

“S7” state: “1011” data

“S8” state: “0011” data

“S9” state: “0001” data

“S10” state: “0000” data

“S11” state: “0100” data

“S12” state: “0110” data

“S13” state: “0010” data

“S14” state: “1010” data

“S15” state: “1110” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operations R4, RG, and R10. The middlepage is determined by read operations R2, R7, R9, and R12. The upperpage is determined by read operations R5, R11, R13, and R15. The toppage is determined by read operations R1, R3, R8, and R14. Therefore,the data allocation of the present example is a 3-4-4-4 coding.

It should be noted that the data allocation to the “S0” to “S15” statesis not limited to the 3-4-4-4 coding. For example, one of the codingsdescribed in the fifth and the sixth embodiments may also be applied.

A conversion operation of the logical page address and the physical pageaddress will be explained with reference to FIG. 76. FIG. 76 is adiagram showing the logical page data allocation with respect to thephysical page.

As shown in FIG. 76, data of the logical first page is dividedrespectively into four pieces of the first cluster to the fourth clusterfrom the head. For example, the memory 100 writes the first cluster ofthe logical first page to the lower page, writes the second cluster ofthe logical first page to the middle page, writes the third cluster ofthe logical first page to the upper page, and writes the fourth clusterof the logical first page to the top page.

11.3 Third Example

A third example of the conversion operation of the logical page addressand the physical page address will be explained.

In the present example, a case of allocating data of two logical pagesto four physical pages (that is, one memory group MG capable of storingfour-page data) will be described.

An example of possible threshold voltage distributions of memory celltransistors MC of the present example will first be described withreference to FIG. 77. FIG. 77 is a diagram showing a relationshipbetween threshold voltage distributions and data allocations of thememory cell transistors MC.

As shown in FIG. 77, in the present example, data is allocated to the“top bit/upper bit/middle bit/lower bit” of each of the memory celltransistors MC that belongs to each of the threshold voltagedistributions in the following manner. Data is allocated to each stateto become a Gray code in which one bit of data changes between twoadjacent states.

“S0” state: “1111” data

“S1” state: “0111” data

“S2” state: “0011” data

“S3” state: “1011” data

“S4” state: “1001” data

“S5” state: “1101” data

“S6” state: “1100” data

“S7” state: “0100” data

“S8” state: “0101” data

“S9” state: “0001” data

“S10” state: “0000” data

“S1l” state: “1000” data

“S12” state: “1010” data

“S13” state: “1110” data

“S14” state: “0110” data

“S15” state: “0010” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operations R6, R8, and R10. The middlepage is determined by read operations R4 and R12. The upper page isdetermined by read operations R2, R5, R9, R13, and R15. The top page isdetermined by read operations R1, R3, R7, R11, and R14. Therefore, thedata allocation of the present example is a 3-2-5-5 coding.

The data allocation to the “S0” to “S15” states is not limited to the3-2-5-5 coding. For example, one of the codings described in the fifthand the sixth embodiments may also be applied. Alternatively, the3-4-4-4 coding described in the second example of the eleventhembodiments may be applied.

The conversion operation of the logical page address and the physicalpage address will be explained with reference to FIG. 78. FIG. 78 is adiagram showing a logical page data allocation with respect to aphysical page.

As shown in FIG. 78, data of the logical first page and the logicalsecond page is divided respectively into two pieces of the first clusterand the second cluster from the head. For example, the memory 100 writesthe first cluster of the logical first page in the lower page, writesthe second cluster of the logical first page in the middle page, writesthe first cluster of the logical second page in the upper page, andwrites the second cluster of the logical second page in the top page.

11.4 Advantageous Effects of Eleventh Embodiment

The configuration of the present embodiment can attain the same effectas the first embodiment.

12. Twelfth Embodiment

A twelfth embodiment will be described. In the twelfth embodiment, acase of applying different codings to first to third cell areas will bedescribed. Hereinafter, the description will focus mainly on mattersdifferent from those of the first to eleventh embodiments.

12.1 Conversion Operation of Logical Page Address and Physical PageAddress

An example of a conversion operation of the logical page address and thephysical page address will first be explained with reference to FIG. 79.FIG. 79 is a diagram showing the logical page data allocation withrespect to the physical page.

In the present embodiment, a case of allocating data of three logicalpages to four physical pages (that is, one memory group MG capable ofstoring four-page data) will be described.

As shown in FIG. 79, data of the logical first page to the logical thirdpage is divided respectively into four pieces of the first cluster tothe fourth cluster from the head. For example, the memory 100 writes thefirst cluster of the logical first page in the first cell area of thelower page, writes the second cluster of the logical first page in thesecond cell area of the lower page, and writes the third cluster of thelogical first page in the third cell area of the lower page. The memory100 writes the fourth cluster of the logical first page in the firstcell area of the middle page, writes the first cluster of the logicalsecond page in the second cell area of the middle page, and writes thesecond cluster of the logical second page in the third cell area of themiddle page. The memory 100 writes the third cluster of the logicalsecond page in the first cell area of the upper page, writes the fourthcluster of the logical second page in the second cell area of the upperpage, and writes the first cluster of the logical third page in thethird cell area of the upper page. The memory 100 writes the secondcluster of the logical third page in the first cell area of the toppage, writes the third cluster of the logical third page in the secondcell area of the top page, and writes the fourth cluster of the logicalthird page in the third cell area of the top page.

12.2 Coding of Memory Cell Transistors

Coding of memory cell transistors MC will be described with reference toFIG. 80. FIG. 80 is a table showing data allocations to each state.

As shown in FIG. 80, in the present embodiment, different codings areapplied in the first to third cell areas. In this case, each of thecodings is selected so that positions of boundaries determining data ofthe logical page become the same among the first cell area, the secondcell area, and the third cell area in a read operation of the logicalpage.

More specifically, in the case of the read operation of the logicalfirst page, positions of the boundary for determining data of the lowerpage and the middle page in the first cell area, positions of theboundary for determining data of the lower page in the second cell area,and positions of the boundary for determining data of the lower page inthe third cell area are the same. Furthermore, in the case of the readoperation of the logical second page, positions of the boundary fordetermining data of the upper page in the first cell area, positions ofthe boundary for determining data of the middle page and the upper pagein the second cell area, and positions of the boundary for determiningdata of the middle page in the third cell area are the same.Furthermore, in the case of the read operation of the logical thirdpage, positions of the boundary for determining data of the top page inthe first cell area, positions of the boundary for determining data ofthe top page in the second cell area, and positions of the boundary fordetermining data of the upper page and the top page in the third cellarea are the same.

For example, in the first cell area, data is allocated to the “topbit/upper bit/middle bit/lower bit” of the memory cell transistor MC inthe following manner.

“S0” state: “1111” data

“S1” state: “1101” data

“S2” state: “0101” data

“S3” state: “0100” data

“S4” state: “0000” data

“S5” state: “1000” data

“S6” state: “1100” data

“S7” state: “1110” data

“S8” state: “1010” data

“S9” state: “0010” data

“S10” state: “0110” data

“S11” state: “0111” data

“S12” state: “0011” data

“S13” state: “1011” data

“S14” state: “1001” data

“S15” state: “0001” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operations R3 and R11. The middle pageis determined by read operations R1, R7, and R14. The upper page isdetermined by read operations R4, R6, R8, R10, and R12. The top page isdetermined by read operations R2, R5, R9, R13, and R15. Therefore, thedata allocation of the the first cell area is a 2-3-5-5 coding.

In the second cell area, data is allocated to the “top bit/upperbit/middle bit/lower bit” of the memory cell transistor MC in thefollowing manner.

“S0” state: “1111” data

“S1” state: “1110” data

“S2” state: “0110” data

“S3” state: “0111” data

“S4” state: “0011” data

“S5” state: “1011” data

“S6” state: “1001” data

“S7” state: “1000” data

“S8” state: “1010” data

“S9” state: “0010” data

“S10” state: “0000” data

“S1l” state: “0001” data

“S12” state: “0101” data

“S13” state: “1101” data

“S14” state: “1100” data

“S15” state: “0100” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operations R1, R3, R7, R11, and R14.The middle page is determined by read operations R6, R8, and R10. Theupper page is determined by read operations RA and R12. The top page isdetermined by read operations R2, R5, R9, R13, and R15. Therefore, thedata allocation of the the second cell area is a 5-3-2-5 coding.

In the third cell area, data is allocated to the “top bit/upperbit/middle bit/lower bit” of the memory cell transistor MC in thefollowing manner.

“S0” state: “1111” data

“S1” state: “1110” data

“S2” state: “0110” data

“S3” state: “0111” data

“S4” state: “0101” data

“S5” state: “0001” data

“S6” state: “0011” data

“S7” state: “0010” data

“S8” state: “0000” data

“S9” state: “1000” data

“S10” state: “1010” data

“S11” state: “1011” data

“S12” state: “1001” data

“S13” state: “1101” data

“S14” state: “1100” data

“S15” state: “0100” data

In the case of reading data that is allocated in the above manner, thelower page is determined by read operations R1, R3, R7, R11, and R14.The middle page is determined by read operations R4, R6, R8, R10, andR12. The upper page is determined by read operations R5 and R13. The toppage is determined by read operations R2, R9, and R15. Therefore, thedata allocation of the third cell area is a 5-5-2-3 coding.

In the case of performing the read operation of the logical first page,the target of the read operation is the first to third cell areas of thelower page and the first cell area of the middle page. In the firstarea, data of the lower page is determined by read operations R3 andR11. Data of the middle page is determined by read operations R1, R7,and R14. In the second cell area, data of the lower page is determinedby R1, R3, R7, R11, and R14. In the third cell area, data of the lowerpage is determined by R1, R3, R7, R11, and R14. Therefore, in all of thefirst cell area, the second cell area, and the third cell area, data ofthe logical first page is determined by read operations R1, R3, R7, R11,and R14. It should be noted that, in the read operation of the logicalfirst page, read voltages may be applied to the selected word line WL inthe order of voltages V1, V3, V7, V11, and V14 or in the order ofvoltages V14, V11, V7, V3, and V1. Furthermore, when read operations R11and R3 are ended, data of the first cluster of the logical first page isdetermined. Therefore, the memory 100 may output this data to theoutside by transferring the data to the latch circuits XDL.

In the case of performing the read operation of the logical second page,the target of the read operation is the second and third cell areas ofthe middle page and the first and second cell areas of the upper page.In the first cell area, data of the upper page is determined by readoperations R4, R6, R8, R10, and R12. In the second cell area, data ofthe middle page is determined by read operations R6, R8, and R10. Dataof the upper page is determined by read operations R4 and R12. In thethird cell area, data of the middle page is determined by readoperations R4, R6, R8, R10, and R12. Therefore, in all of the first cellarea, the second cell area, and the third cell area, data of the logicalsecond page is determined by read operations R4, R6, R8, R10, and R12.It should be noted that, in the read operation of the logical secondpage, read voltages may be applied to the selected word line WL in theorder of voltages V4, V6, V8, V10, and V12, or in the order of voltagesV12, V10, V8, VG, and V4. Furthermore, when read operations R6, R8, andR10 are ended, data of the first cluster of the logical second page isdetermined. Therefore, the memory 100 may output this data to theoutside by transferring the data to the XDL. Furthermore, when readoperations R4 and R12 are ended, data of the fourth cluster of thelogical second page is determined. Therefore, the memory 100 may outputthis data to the outside by transferring the data to the latch circuitsXDL. In this case, for example, in the memory 100, the allocation of thefirst cluster of the logical second page and the allocation of thefourth cluster of the logical second page explained with reference toFIG. 79 may be switched. By switching the allocations, the memory 100can output to the outside data of the first cluster of the logicalsecond page earlier than before switching the allocations.

In the case of performing the read operation of the logical third page,the target of the read operation is the third cell area of the upperpage and the first to third cell areas of the top page. In the firstcell area, data of the top page is determined by read operations R2, R5,R9, R13, and R15. In the second cell area, data of the top page isdetermined by read operations R2, R5, R9, R13, and R15. In the thirdcell area, data of the upper page is determined by read operations R5and R13. Data of the top page is determined by read operations R2, R9,and R15. Therefore, in all of the first cell area, the second cell area,and the third cell area, data of the logical third page is determined byread operations R2, R5, R9, R13, and R15. It should be noted that, inthe read operation of the logical third page, read voltages may beapplied to the selected word line WL in the order of voltages V2, V5,V9, V13, and V15, or in the order of voltages V15, V13, V9, V5, and V2.When read operations R13 and R5 are ended, data of the first cluster ofthe logical third page is determined. Therefore, the memory 100 mayoutput this data to the outside by transferring the data to the latchcircuits XDL.

12.3 Advantageous Effects of Twelfth Embodiment

According to the configurations of the present embodiment, it ispossible to obtain effects similar to those of the first and tenthembodiments. For example, in the case of the present embodiment, data ofthe logical first page, data of the logical second page, and data of thelogical third page can be determined by performing the read operationfive times, respectively.

13. Thirteenth Embodiment

A thirteenth embodiment will be described. In the thirteenth embodiment,an example in which two memory cell transistors MC are used to store3-bit data will be explained. Hereinafter, the description will focusmainly on matters different from those of the first to twelfthembodiments.

13.1 Threshold Voltage Distributions of Memory Cell Transistors

Possible threshold voltage distributions of memory cell transistors MCwill first be described with reference to FIG. 81. FIG. 81 is a diagramshowing threshold voltage distributions of the memory cell transistorsMC.

As shown in FIG. 81, the threshold voltage of each memory celltransistor MC takes a value that falls within, for example, threediscrete distributions. That is, the memory cell transistor MC of thepresent embodiment is a 1.5 bit/Cell that can hold three values of data.Hereinafter, the three distributions will be respectively referred toas, in ascending order of threshold voltage, an “S0” state, an “S1”state, and an “S2” state.

The “S0” state corresponds to, for example, a data erase state. The “S1”and “S2” states correspond to states in which a charge is injected intothe charge storage layer and data is written. In the write operation, itis assumed that verify voltages corresponding to the respectivethreshold voltage distributions are V1 and V2. In this case, the voltagevalues establish a relationship of V1<V2<Vread.

It should be noted that setting values for the verify voltages andsetting values for read voltages corresponding to the respective statesmay be either identical to or different from each other. To simplify thedescription, a case will be described in which the setting values forthe verify voltages and the setting values for the read voltages are thesame.

Hereinafter, read operations corresponding to the read operations of the“S1” and “S2” states will be respectively referred to as read operationsR1 and R2. In read operation R1, it is determined whether or not thethreshold voltage of the memory cell transistor MC is less than thevoltage V1. In read operation R2, it is determined whether or not thethreshold voltage of the memory cell transistor MC is less than thevoltage V2.

Hereinafter, data corresponding to read operation R1 (read voltage V1)will be referred to as “V1 data”, and data corresponding to readoperation R2 (read voltage V2) will be referred to as “V2 data”.

As described above, each memory cell transistor MC belongs to one of thethree threshold voltage distributions, thereby taking one of the threestates.

13.2 Coding

Coding will be described with reference to FIG. 82. FIG. 82 is a tableshowing data allocations by two memory cell transistors MC.

In the present embodiment, a set of two memory cell transistors MC(hereinafter also referred to as a “cell unit”) holds eight values(three bits) of data. Accordingly, the memory cell array 130 isconfigured by 3 bit/2 Cell (hereinafter also referred to as “D1.5 (threevalues)”). Hereinafter, the two memory cell transistors MC configuring acell unit will be referred to as an “A cell” and a “B cell”,respectively. In the present embodiment, the memory cell transistor MCincluded in the first cell area functions as the “A cell”, and thememory cell transistor MC included in the second cell area functions asthe “B cell”. Furthermore, a unit of data collectively written withrespect to a plurality of cell units will be referred to as a “section”.For example, in a case of writing data of one section, the size (datalength) of the section is ½ of the number of memory cell transistors MCincluded in one memory group MG. That is, the size of the section is ½of a page size of a physical page.

By allocating states of eight values of the cell unit to “000” to “111”in binary notation, the cell unit is capable of storing three bits ofdata. Hereinafter, the three bits of data stored by the cell unit willbe referred to respectively as a “first bit of a cell unit”, a “secondbit of a cell unit”, and a “third bit of a cell unit”. Furthermore, agroup of the first bit of a cell unit, a group of the second bit of acell unit, and a group of the third bit of a cell unit to becollectively written in (or read from) the memory group MG will bereferred to as a “first section”, a “second section”, and a “thirdsection”, respectively.

In the example of FIG. 82, with respect to the combinations of thestates of the “A cell/B cell”, data is allocated to the “first section(first bit of a cell unit)/second section (second bit of a cellunit)/third section (third bit of a cell unit)” in the following manner.

“S0/S0” state: “111” data

“S0/S1” state: “100” data

“S0/S2” state: “000” data

“S1/S0” state: “110” data

“S1/S1” state: “101” data

“S1/S2” state: “001” data

“S2/S0” state: “010” data

“S2/S1” state: “011” data

The states of the three bits are described in the manner above by thecombination of the states of the A cell and B cell. It should be notedthat a case of A cell/B cell=“S2/S2” is defined as not to be used.

A bit value of the first section (first bit of the cell unit) isdetermined by read operation R2 (read voltage V2) in the A cell (firstcell area) and read operation R2 (read voltage V2) in the B cell (secondcell area). In the case where the A cell or the B cell is in the “S2”state, “0” is allocated to the bit value of the first section.

A bit value of the second section (second bit of the cell unit) isdetermined by read operation R2 (read voltage V2) in the A cell (firstcell area) and read operation R1 (read voltage V1) in the B cell (secondcell area). In the case where the A cell is in the “S0” or “S1” state,and the B cell is in the “S1” or “S2” state, “0” is allocated to the bitvalue of the second section.

A bit value of the third section (third bit of the cell unit) isdetermined by read operation R1 (read voltage V1) in the A cell (firstcell area) and read operation R1 (read voltage V1) in the B cell (secondcell area). In the case where the A cell is in the “S0” state and the Bcell is in the “S1” or “S2” state, or in the case where the A cell is inthe “S1” or “S2” state and the B cell is is the “S0” state, “0” isallocated to the bit value of the third section.

13.3 Calculations of Bit Values of Sections

Calculations of the bit values of the sections will be described withreference to FIG. 83. FIG. 83 is a diagram showing the relationshipbetween data allocations to the A cell and the B cell and bit values ofthe sections. In the example of FIG. 83, “&” indicates an AND operation,and “˜” indicates negation of data.

As shown in FIG. 83, in read operation R1 of the A cell or the B cell,in a case where the threshold voltage is equal to or larger than readvoltage V1, “0” data is allocated as the V1 data, and, in a case wherethe threshold voltage is less than read voltage V1, “1” data isallocated as the V1 data. Furthermore, in read operation R2 of the Acell or the B cell, in a case where the threshold voltage is equal to orlarger than read voltage V2, “0” data is allocated as the V2 data, and,in a case where the threshold voltage is less than read voltage V2, “1”data is allocated as the V2 data. The bit value of each section may thenbe calculated by the following operations.

The bit value of the first section is calculated by an exclusive NOR(EXNOR) operation of a read result (V2 data) of the A cell using readvoltage V2 and a read result (V2 data) of the B cell using read voltageV2.

The bit value of the second section is calculated by a NAND operation ofa read result (V2 data) of the A cell using read voltage V2 and anegative of a read result (V1 data) of the B cell using read voltage V1.

The bit value of the third section is calculated by an EXNOR operationof a read result (V1 data) of the A cell using read voltage V1 and aread result (V1 data) of the B cell using read voltage V1.

13.4 Conversion Operation of Logical Page Address and Physical PageAddress

An example of a conversion operation of the logical page address and thephysical page address will be explained with reference to FIGS. 84 and85. FIG. 84 is a diagram explaining a flow of the conversion operationof the logical page address and the physical page address. FIG. 85 is adiagram showing the logical page data allocation with respect to thephysical page.

In the present embodiment, a case in which data of one logical page isallocated to three sections in one memory group MG will be explained.

As shown in FIG. 84, for example, when the memory controller 200receives a write request from the host device 2, it allocates onelogical page address “90001” (logical first page) corresponding to onereceived logical address “00001”.

When the command user interface circuit 121 receives a write orderincluding one page of the logical page address and the logical page fromthe memory controller 200, the command user interface circuit 121converts the one page of the logical page address into three sections ofthe physical page address in accordance with a preset mapping. At thistime, a data length of one page of the logical page and a data length ofthe three sections are the same.

The page size of one logical page will be referred to as “m” (“m” is anumber equal to or greater than one), and the number of logical pages tobe written (that is, the number of logical page addresses included inthe order) will be referred to as “a” (“a” is an integer equal to orgreater than one). Furthermore, the page size of the physical page ofone memory group MG will be referred to as “n” (“n” is a number smallerthan “m”), and the number of sections (that is, the number of bits ofdata that is being stored in the set of A cell and B cell) will bereferred to as “c” (“c” is an integer larger than “a”). Since the pagesize n of one physical page doubles the size of the section (the numberof cell units), n may be described by n=m×2 a/c. In the presentembodiment, since a=1 and c=3, the page size of the physical page isn=m×⅔. For example, in the case where the page size of the logical pageis 16 [kB], the page size of the physical page is n=16×⅔=10.67 [kB]. Inthis case, the number of memory cell transistors MC that can satisfy theequation for the page size n=10.67 [kB] of one physical page is aninteger equal to or greater than the integer calculated by rounding updigits after the decimal point of 10.67×1024. In other words, the numberof memory cell transistors MC is equal to or greater than the integercalculated by rounding up digits after the decimal point of the pagesize of one physical page.

The arrangement of the logical page data in one memory group MG will bedescribed in detail.

As shown in FIG. 85, data of the logical first page is divided intothree pieces of the first cluster to the third cluster from the head.For example, the memory 100 writes data of the first cluster in thefirst section, writes data of the second cluster in the second section,and writes data of the third cluster in the third section. In thepresent embodiment, the data of the first section corresponds to the,data of the first cluster of the logical first page, the data of thesecond section corresponds to the data of the second cluster of thelogical first page, and the data of the third section corresponds to thedata of the third cluster of the logical first page.

13.5 Configurations of Sense Amplifier and Page Buffer

Configurations of the sense amplifier 132 and the page buffer 133 willbe briefly described. The memory cell array 130 of the presentembodiment is configured by the 3 bit/2 Cell that is a set of the A cellof the first cell area and the B cell of the second cell area.Accordingly, as explained in the first example of the ninth embodimentwith reference to FIG. 69, the preferred configuration of the senseamplifier 132 and the page buffer 133 is a configuration in which thesense amplifier units SAU1 and SAU2 are arranged alternately. This isbecause, when computing the data of the A cell and the B cell, it iseasier to design the corresponding sense circuits SA and latch circuitsXDL, ADL, and BDL, etc. in a physically close arrangement.

13.6 Read Operation

The read operation will be explained. In the read operation of thepresent embodiment, when the memory 100 receives a read order based onthe logical page from the memory controller 200, the memory 100 readsdata from a plurality of physical pages corresponding thereto, computesthe read data to calculate sections, then combines the sections tooutput them as data of the logical page.

13.6.1 Flow of Read Operation

The flow of the read operation in the memory 100 will first be describedwith reference to FIGS. 86 and 87. FIGS. 86 and 87 are flowcharts of theread operation.

As shown in FIGS. 86 and 87, the memory 100 receives a read order of thelogical first page from the memory controller 200 (step S1) The commanduser interface circuit 121 converts the logical page address into thephysical page addresses, then transmits the received command and theconverted physical page addresses to the sequencer 123.

The sequencer 123 first executes read operation R2 corresponding to readvoltage V2 (step S90).

The sequencer 123 transfers the data (V2 data) read by sense circuitsSA1 and SA2 to latch circuits BDL1 and BDL2, respectively (step S91).

The sequencer 123 performs arithmetic processing using data in the latchcircuits BDL1 (V2 data of the A cell) and data in the latch circuitsBDL2 (V2 data of the B cell), and calculates data of the first section(data of the first cluster of the logical first page) (step S92).

The sequencer 123 transfers the calculated data of the first section tothe latch circuits XDL1 (step S93).

The sequencer 123 executes read operation R1 corresponding to readvoltage V1 (step S94).

The sequencer 123 transfers the data (V1 data) read by the sensecircuits SA1 and SA2 to latch circuits ADL1 and ADL2, respectively (stepS95).

The sequencer 123 performs arithmetic processing using data in the latchcircuits BDL1 (V2 data of the A cell) and data in the latch circuitsADL2 (V1 data of the B cell), and calculates data of the second section(data of the second cluster of the logical first page) (step S96).

The sequencer 123 transfers the calculated data of the second section tothe latch circuits XDL2 (step S97).

The sequencer 123 performs arithmetic processing using data in the latchcircuits ADL1 (V1 data of the A cell) and data in the latch circuitsADL2 (V1 data of the B cell), and calculates data of the third section(data of the third cluster of the logical first page) (step S98).

The sequencer 123 transfers the calculated data of the third section tothe latch circuits BDL1 (step S99).

The sequencer 123 sets a head address of the latch circuit XDL1 as acolumn address CA in a column counter 125 (step S100). Based on thecolumn address CA incremented by the column counter 125, the serialaccess controller 126 receives data sequentially from the head addressof the latch circuit XDL1 and transfers it to an input/output circuit110. The input/output circuit 110 starts transmitting (outputting) thedata in the latch circuits XDL1 (data of the first cluster of thelogical first page) to the memory controller 200.

In the case where the data output of the latch circuits XDL1 is notended (step S101_No), the sequencer 123 repeats a confirmation operationof the data output until the output is ended.

When the data output of the latch circuits XDL1 is ended (stepS101_Yes), the sequencer 123 transfers the data in the latch circuitsBDL1 to the latch circuits XDL1 (step S102). Furthermore, when the dataoutput of circuits XDL1 is ended, data output of the latch circuits XDL2(data of the second cluster of the logical first page) is startedsubsequently.

In the case where the data output of the latch circuits XDL2 is notended (step S103_No), the sequencer 123 repeats a confirmation operationof the data output until the output is ended.

When the data output of the latch circuits XDL2 is ended (stepS103_Yes), a head address of the latch circuit XDL1 is set as a columnaddress CA in the column counter 125 (step S104). Based on the columnaddress CA incremented by the column counter 125, the serial accesscontroller 126 receives data sequentially from the head address of thelatch circuit XDL1 and transfers it to an input/output circuit 110. Theinput/output circuit 110 starts transmitting (outputting) the data inthe latch circuits XDL1 (data of the third cluster of the logical firstpage) to the memory controller 200. When the data output of the latchcircuits XDL1 is ended, the sequencer 123 ends the read operation of thelogical first page. It should be noted that, the data of the firstsection is determined while executing read operation R1 after readoperation R2 is ended. Therefore, the memory 100 may set the externalRBn signal to the “H” level and output the data.

13.6.2 Command Sequence of Read Operation

An example of a command sequence of the read operation will be describedwith reference to FIG. 88. FIG. 88 is a command sequence of the readoperation of the logical first page. In the example of FIG. 88, signalsCEn, CLE, ALE, WEn, and REn are omitted to simplify the description. Inthe example of FIG. 88, some of the commands and addresses are omitted.In addition, the example of FIG. 88 also shows voltages of the selectedword line WL in a case where the internal RBn signal is in the busystate.

As shown in FIG. 88, when the sequencer 123 receives a command “30h”, itstarts the read operation in response to the command. The sequencer 123first sets the internal RBn signal and the external RBn signal to the“L” level indicating the busy state. The sequencer 123 then executesread operation R2. That is, read voltage V2 is applied to the selectedword line WL. The result of reading data (V2 data) is stored in thelatch circuits BDL1 (corresponding to the A cell) and BDL2(corresponding to the B cell)

After read operation R2 is ended, the sequencer 123 executes readoperation R1. That is, read voltage V1 is applied to the selected wordline WL. The result of reading data (V1 data) is stored in the latchcircuits ADL1 (corresponding to the A cell) and ADL2 (corresponding tothe B cell).

While read operation R1 is being executed, the sequencer 123 performsarithmetic processing using data in the latch circuits BDL1 and data inthe latch circuits BDL2, and calculates data of the first section. Thecalculated data is stored in the latch circuits XDL1.

When read operation R1 is ended, the sequencer 123 sets the internal RBnsignal and the external RBn signal to the “H” level indicating the readystate. Furthermore, the sequencer 123 performs arithmetic processingusing data in the latch circuits BDL1 and data in the latch circuitsADL2, and calculates data of the second section. The calculated data isstored in the latch circuits XDL2.

When the “H” level external RBn signal is received, the memorycontroller 200 transmits signal REn (not shown) to the memory 100. Theinput/output circuit 110 starts outputting data in accordance withsignal REn. The input/output circuit 110 first outputs data in the latchcircuits XDL1 (data of the first cluster of the logical first page).

While the data in the latch circuits XDL1 is being output, the sequencer123 performs arithmetic processing using data in the latch circuits ADL1and data in the latch circuits ADL2, and calculates data of the thirdsection. The calculated data is stored in the latch circuits BDL1.

When data output of the latch circuits XDL1 is ended, data in the latchcircuits BDL1 is transferred to the latch circuits XDL1. In successionto the latch circuits XDL1, the input/output circuit 110 outputs data inthe latch circuits XDL2 (data of the second cluster of the logical firstpage). Furthermore, in succession to the latch circuits XDL2, theinput/output circuit 110 outputs data in the latch circuits XDL1 (dataof the third cluster of the logical first page). When data output of thelatch circuits XDL1 is ended, the read operation of the logical firstpage is ended.

It should be noted that the order in which read voltages V1 and V2 areapplied may be switched. Furthermore, in the case where the data outputof the latch circuits XDL2 is ended before storing the data of the thirdsection in the latch circuits BDL1, the sequencer 123 may temporarilyset the external RBn signal to the “L” level and suspend the dataoutput. It should be noted that, the data of the first section isdetermined while executing read operation R1 after read operation R2 isended. Therefore, the memory 100 may set the external RBn signal to the“H” level and output the data.

13.7 Write Operation

The write operation will be described. In the present embodiment, thefull sequence write operation is executed in which the data of the firstto the third sections is collectively written in the memory group MG. Inother words, in the full sequence write operation of the presentembodiment, the “S1” and “S2” states are written.

13.7.1 Flow of Write Operation

The flow of the write operation in the memory 100 will be described withreference to FIGS. 89 and 90. FIGS. 89 and 90 are flowcharts of thewrite operation.

As shown in FIGS. 89 and 90, when receiving a write order, the memory100 receives the logical page address of the logical first page from thememory controller 200 (step S280). The command user interface circuit121 converts the logical page address of the logical first page into thephysical page addresses.

The sequencer 123 sets a head address of the latch circuit XDL1 as acolumn address CA in the column counter 125 (step S281).

In the page buffer 133, data input of the first cluster of the logicalfirst page to the latch circuits XDL1 is started based on the columnaddress CA received from the column counter 125 (step S282).

In the case where the data input of the latch circuits XDL1 is not ended(step S283_No), the sequencer 123 repeats a confirmation operation ofthe data input until the input is ended.

When the data input to the latch circuits XDL1 is ended (step S283_Yes),the sequencer 123 transfers the data in the latch circuits XDL1 to thelatch circuits BDL1 (step S284).

Furthermore, when the data input to the latch circuits XDL1 is ended,data input of a second cluster of the logical first page to the latchcircuits XDL2 is started subsequently. It should be noted that, in thecase of step S283_Yes, the data input of the second cluster of thelogical first page to the latch circuits XDL2 may be startedsubsequently, and the sequencer 123 may execute step S284 during thedata input.

In the case where the data input of the latch circuits XDL2 is not ended(step S285_No), the sequencer 123 repeats a confirmation operation ofthe data input until the input is ended.

When the data input to the latch circuits XDL2 is ended (step S285_Yes),the sequencer 123 transfers the data in the latch circuits XDL2 to thelatch circuits BDL2 (step S286).

The sequencer 123 sets a head address of the latch circuit XDL1 as acolumn address CA in the column counter 125 (step S287). In the pagebuffer 133, data input of a third cluster of the logical first page tothe latch circuits XDL1 is started based on the column address CAreceived from the column counter 125. It should be noted that, in thecase of step S285_Yes, the data input of the third cluster of thelogical first page to the latch circuits XDL1 may be startedsubsequently, and the sequencer 123 may execute step S286 during thedata input.

In the case where the data input of the latch circuits XDL1 is not ended(step S288_No), the sequencer 123 repeats a confirmation operation ofthe data input until the input is ended.

When the data input to the latch circuits XDL1 is ended (step S288_Yes),the data input of the logical first page to the latch circuits XDL1 andXDL2 is ended. The sequencer 123 sets the external RBn signal and theinternal RBn signal to the “L” level.

The sequencer 123 computes the data in the latch circuits BDL1, BDL2,and XDL1, that is, the data of the first section, the second section,and the third section, and calculates V1 data of the A cell and the Bcell (step S289). The calculated V1 data of the A cell and the B cell istransferred to the latch circuits ADL1 and ADL2, respectively (stepS290).

The sequencer 123 computes the data in the latch circuits BDL1, BDL2,and XDL1, that is, the data of the first section, the second section,and the third section, and calculates V2 data of the A cell and the Bcell (step S291). The calculated V2 data of the A cell and the B cell istransferred to the latch circuits XDL1 and XDL2, respectively (stepS292). At this time, the data of the third section is stored in thelatch circuit XDL1; however, this may be overwritten with V2 data of theA cell. The sequencer 123 determines the state of each of the memorycell transistors MC based on the combination of data in the latchcircuits ADL1, ADL2, XDL1, and XDL2.

The sequencer 123 executes the program operation based on the determinedstates (step S293).

After ending the program operation, the sequencer 123 executes theprogram verify operation (step S294).

In the case where the verification is not passed (step S295_No), thesequencer 123 confirms whether or not the number of program loops hasreached a preset upper limit number (step S296)

In the case where the number of program loops has not reached the upperlimit number (step S296_No), the sequencer 123 executes the programoperation (step S293). That is, the sequencer 123 repeats the programloop.

In the case where the number of program loops has reached the upperlimit number (step S296_Yes), the sequencer 123 ends the write operationand reports to the memory controller 200 that the write operation didnot end successfully.

In the case of passing the verification (step S295_Yes), that is, endingwriting of the “S1” and “S2” states, the sequencer 123 sets the externalRBn signal to the “H” level and ends the full sequence write operation.

13.7.2 Command Sequence of Write Operation

An example of a command sequence of the write operation will bedescribed with reference to FIG. 91. FIG. 91 is a command sequence ofthe full sequence write operation. In the example of FIG. 91, signalsCEn, CLE, ALE, WEn, and REn are omitted to simplify the description.

As shown in FIG. 91, the memory controller 200 first transmits a command“80h” to the memory 100. The memory controller 200 then transmits alogical page address “AD-P1” of the logical first page. In the memory100, the command user interface circuit 121 converts the receivedlogical page address “AD-P1” into the physical page addresses. Thememory controller 200 then transmits data of the logical first page tothe memory 100. The first cluster of the logical first page is stored inthe latch circuits XDL1, and is then transferred to the latch circuitsBDL1. The second cluster of the logical first page is then stored in thelatch circuits XDL2, and is then transferred to the latch circuits BDL2.The third cluster of the logical first page is stored in the latchcircuits XDL1

The memory controller 200 then transmits a command “10h” to the memory100.

When the command “10h” is received, the sequencer 123 sets the internalRBn signal and the external RBn signal to the “L” level.

The sequencer 123 calculates V1 data based on the data stored in thelatch circuits BDL1, BDL2, and XDL1, and stores the result in the latchcircuits ADL1 and ADL2. In addition, the sequencer 123 calculates V2data based on the data stored in the latch circuits BDL1, BDL2, andXDL1, and stores the result in the latch circuits XDL1 and XDL2. Thesequencer 123 determines the state of each of the memory celltransistors MC based on the combination of the data in the latchcircuits ADL1, ADL2, XDL1, and XDL2, and executes the write operation.After ending the write operation, the sequencer 123 sets the internalRBn signal and the external RBn signal to the “H” level.

13.8 Advantageous Effects of Thirteenth Embodiment

The configurations of the present embodiment can attain the same effectas the first embodiment.

For example, in some cases, the memory 100 may include a multivalued (2to 4 bit/Cell) memory area and a high-speed and high-reliability memoryarea. For example, the high-speed and high-reliability memory area isused for speeding up access or enhancing reliability of data, and storesdata as a binary value (1 bit/Cell). The high-speed and high-reliabilitymemory area of the first to twelfth embodiments can be in a binary value(1 bit/Cell). However, since the page size of a physical page of themultivalued memory area is smaller than that of a logical page, thelogical page of the high-speed and high-reliability memory area wouldbecome small. In such a case, the first to twelfth embodiments maybeapplied to the multivalued memory area, and the present embodiment maybe applied to the high-speed and high-reliability memory area. Thisallows the page size of the logical page of the multivalued memory areaand the page size of the logical page of the high-speed andhigh-reliability memory area to become the same.

It should be noted that an allocation of data storing three bits in 2cell 3 value is described in, for example, U.S. patent application Ser.No. 16/123,162 filed on Sep. 6, 2018, entitled “SEMICONDUCTOR MEMORY”.The entire contents of this patent application are incorporated hereinby reference.

Furthermore, in the present embodiment, a case in which the memory celltransistor MC holds data of three bits in 3 value 2 cell (1.5 bit/Cell)is described; however, the present embodiment is not limited thereto.For example, the memory cell transistor MC may hold five bits of data in6 value 2 cell (2.5 bit/Cell), may hold seven bits of data in 12 value 2cell (3.5 bit/Cell), or may hold nine bits of data in 23 value or 24value 2 cell (4.5 bit/Cell).

14. Modifications, etc.

The semiconductor memory according to the above embodiments includes: amemory group (MG) including a plurality of memory cells (MC) configuredto store a plurality of bits of data in three or more plurality ofstates; a word line (WL) coupled to the plurality of memory cells; and afirst circuit (121) configured to convert one external address (logicalpage address) received from an external controller (200) into aplurality of internal addresses (physical page addresses), wherein afirst page size of page data (data of the physical page) of the memorygroup is smaller than a second page size of input data (data of thelogical page) corresponding to the external address.

By applying the above embodiments, it is possible to provide asemiconductor memory that can suppress an increase in a chip area.

It should be noted that the embodiments are not limited to theabove-described aspects, and various modifications may be adoptedtherein.

For example, in each coding, “0” data and “1” data may be inverted.

For example, in the first to twelfth embodiments, an example of thememory cell transistor MC being 2 to 4 bit/Cell has been described;however the memory cell transistor MC is not limited to this. Forexample, the memory cell transistor MC may be 5 bit/Cell. Furthermore,the memory cell transistor MC may hold five bits of data in 6 value 2cell (2.5 bit/Cell), may hold seven bits of data in 12 value 2 cell (3.5bit/Cell), or may hold nine bits of data in 23 value or 24 value 2 cell(4.5 bit/Cell).

For example, the memory 100 is not limited to a NAND flash memory. Thememory 100 should be a non-volatile memory that performs a readoperation or a write operation by selecting only addresses of some wordlines within an address space of the memory cell array. For example, thememory 100 may be a phase change memory (PCM), a magnetoresistive randomaccess memory (MRAM), or a ferroelectric random access memory (FeRAM).

Furthermore, in the first to twelfth embodiments, data is written instates of eight values or 16 values in one write operation; however, inorder to suppress influence from adjacent memory cell transistors, thewriting operation may be performed in, for example, two writing steps.In this case, if the influence from adjacent memory cell transistors issignificant, after a write operation of a first page of a first wordline (WLn) is performed, a write operation of a first page of anadjacent second word line (WLn+1) is executed, and a write operation ofa second page of the first word line (WLn) is performed thereafter. Forexample, in the case of the tenth embodiment, as shown in FIG. 92, whenthe write operation of the logical first page is performed, the memorycell transistor MC of the first cell area is written in the state S0,S2, S4, or S6 when data of the first cluster of the logical first pageis written in the lower page and data of the third cluster of thelogical first page is written in the middle page. On the other hand, thememory cell transistor MC of the second cell area is written in thestate S0or S2 when data of the second cluster of the logical first pageis written in the lower page. It should be noted that the state of thewrite operation of the logical first page may be lower than the state ofthe write operation of the logical second page. Furthermore, a step-upvoltage amount of the write operation of the logical first page may begreater than that of the write operation of the logical second page.Subsequently, when performing the write operation of the logical secondpage, data written by the write operation of the logical first page isread by an internal read operation. Then, when data of the secondcluster of the logical second page is written in the upper page, thememory cell transistor MC of the first cell area is written in the stateS0or S1 in the case where data is written in the state S0, is written inthe state S2 or S3 in the case where data is written in the state S2, iswritten in the state S4 or S5 in the case where data is written in thestate S4, and is written in the state S6 or S7 in the case where data iswritten in the state S6. When data of the first cluster of the logicalsecond page is written in the middle page and data of the third clusterof the logical second page is written in the upper page, the memory celltransistor MC of the second cell area is written in the state S0, S1,S4, or S5 in the case where data is written in the state S0, and iswritten in the state S2, S3, S6, or S7 in the case where data is writtenin the state S2. It should be noted that if a read operation isperformed after the write operation of the logical first page prior tothe write operation of the logical second page, data will be incorrectsince data is not written in the Vth distribution after the writeoperation of the logical second page. Therefore, a read command for thismay be provided separately, or a flag cell may be prepared for each pageto change the read level.

For example, the above-described embodiments may be combined whereverpossible.

Furthermore, the term “couple” in the above-described embodimentsincludes indirect coupling via a transistor or a resistor, etc.

The embodiments are only examples, and therefore do not limit the scopeof the invention.

What is claimed is:
 1. A semiconductor memory comprising: a memory groupincluding a plurality of memory cells configured to store a plurality ofbits of data in three or more plurality of states; a word line coupledto the plurality of memory cells; and a first circuit configured toconvert one external address received from an external controller into aplurality of internal addresses, wherein a first page size of page dataof the memory group is smaller than a second page size of input datacorresponding to the external address.
 2. The semiconductor memoryaccording to claim 1, wherein the input data is written in at least twobits of a part of the plurality of memory cells.
 3. The semiconductormemory according to claim 1, wherein, when the second page size isdescribed as “m”, the number of pages of the input data included in anorder received from the external controller is described as “a”, thenumber of pages of the page data of the memory group is described as“b”, and the first page size is described as “n”, n=m×a/b isestablished.
 4. The semiconductor memory according to claim 1, wherein,in a read operation, a plurality of pages of the page data are read fromthe memory group, and at least a part of the plurality of pages of thepage data is combined and output.
 5. The semiconductor memory accordingto claim 1, wherein at least one bit of the plurality of bits of theplurality of memory cells is determined by one read operation using oneread voltage.
 6. A semiconductor memory comprising: a memory groupincluding a plurality of first memory cells and a plurality of secondmemory cells; a word line coupled to the plurality of first memory cellsand the plurality of second memory cells; and a first circuit configuredto convert one external address received from an external controllerinto a plurality of internal addresses, wherein a first page size ofpage data of the memory group is smaller than a second page size ofinput data corresponding to the external address, and a set of one ofthe plurality of first memory cells and one of the plurality of secondmemory cells is configured to store a plurality of bits of data.
 7. Thesemiconductor memory according to claim 6, wherein, when the second pagesize is described as “m”, the number of pages of the input data includedin an order received from the external controller is described as “a”,the number of bits of data that is being capable of storing in the setis described as “c”, and the first page size is described as “n”, n=m×2a/c is established.
 8. A nonvolatile memory comprising: a plurality ofmemory cells configured to store three bits of data described by firstto third bits and allocated to eight threshold areas that include afirst threshold area indicating an erase area and second to eighththreshold areas each indicating write areas, the threshold voltages ofthe the second to eighth threshold areas being higher than a thresholdvoltage of the first threshold area, the g-th threshold area (g is anatural number from two to eight) indicating one of the second to eighththreshold areas having a higher threshold voltage than the (g−1)-ththreshold area; a word line coupled to the plurality of memory cells;and a controller configured to execute a read operation with respect tothe plurality of memory cells in response to a read command from anexternal controller, wherein among first to seventh voltages existingbetween adjacent threshold areas of the first to eighth threshold areas,the number of voltages used for determining a value of data of the firstbit is one, the number of voltages used for determining a value of dataof the second bit is p (p is a natural number from two to four), and thenumber of voltages used for determining a value of data of the third bitis (6−p), an address specified by the read command corresponds to one ofa first page address and a second page address, in a case where thespecified address corresponds to the first page address, the controlleris configured to read data from the plurality of memory cells by using avoltage used for determining the value of data of the first bit and thep voltages used for determining the value of data of the second bitamong the first to seventh voltages, and in a case where the specifiedaddress corresponds to the second page address, the controller isconfigured to read data from the plurality of memory cells by using avoltage used for determining the value of data of the first bit and the(6−p) voltages used for determining the value of data of the third bitamong the first to seventh voltages.
 9. The nonvolatile memory accordingto claim 8, wherein the h-th voltage (h is a natural number from two toseven) is higher than the (h−1)-th voltage, and the fourth voltage isthe voltage used for determining the value of data of the first bit. 10.The nonvolatile memory according to claim 9, wherein the p is three. 11.The nonvolatile memory according to claim 10, wherein the first voltage,the third voltage, and the sixth voltage are used for determining thevalue of data of the second bit, and the second voltage, the fifthvoltage, and the seventh voltage are used for determining the value ofdata of the third bit.
 12. The nonvolatile memory according to claim 9,wherein the p is four.
 13. The nonvolatile memory according to claim 12,wherein the first voltage, the third voltage, the fifth voltage, and theseventh voltage are used for determining the value of data of the secondbit, and the second voltage and the sixth voltage are used fordetermining the value of data of the third bit.
 14. The nonvolatilememory according to claim 9, wherein the p is two.
 15. The nonvolatilememory according to claim 14, wherein the second voltage and the sixthvoltage are used for determining the value of data of the second bit,and the first voltage, the third voltage, the fifth voltage, and theseventh voltage are used for determining the value of data of the thirdbit.